You are asked to design an NMOS inverter with a resistive load, as shown in Figure 2.e, with the input voltage of either 0 V (logic level 0) or 3.3 V (logie level 1). The transistor is an n-channel...

Extracted text: You are asked to design an NMOS inverter with a resistive load, as shown in Figure 2.e, with the input voltage of either 0 V (logic level 0) or 3.3 V (logie level 1). The transistor is an n-channel enhancement type MOSFET with a threshold voltage of Vr = 1.5 V, an aspect ratio (WIL) of 20, and a gate capacitor per unit arca of 400 nF/em. The electron mobility is 500 cm/Vs. When the input is at logic level 1 (v, = 3.3 V), the transistor is in the linear region. Find the values of Voo and Rp to have the output voltage of 0.3 V at logic level 0 and 3.3 V at logic level +Vpo Rp O Va 1. Figure 2.e.