30/10/2019 https://athena.ecs.csus.edu/~changw/205/prg/3/ https://athena.ecs.csus.edu/~changw/205/prg/3/ 1/3 CSc 205 Verilog Programming #3: Adder-Subtractor (Arrays of Gates & Modules) 1. In this...

1 answer below »
Write a Verilog program to simulate a 5-bit adder-subtractor.


30/10/2019 https://athena.ecs.csus.edu/~changw/205/prg/3/ https://athena.ecs.csus.edu/~changw/205/prg/3/ 1/3 CSc 205 Verilog Programming #3: Adder-Subtractor (Arrays of Gates & Modules) 1. In this programming assignment, we will practice the use of modules as an array! 2. Write a Verilog program to simulate a 5-bit adder-subtractor. Submit only 1 program file "add-sub.v" to your "3rdPrgAssig" folder. (Make a "V2" folder for revision 2, in the same folder to re-submit. Use "V3" for another revision, and so on.) Misplaced files may get points deducted. 3. A single Full Adder (FA) is illustrated below. Make the final simulated based on a 5-bit adder- subtractor which will have five FA's chained. The five xor gates are used to flip y bits when performing a subtraction. The 6th xor gate is used to detect an overflow condition (explained below). 4. The first carry-in bit C0 can serve as the flag to perform a subtraction if set 1. If 0, it performs addition. The truth table shows the s (sum) and cout (carry-out) bits are results of a majority function and parity check: cin x y -> cout s 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 Follow the diagram below to program a Full Adder. Multi-bit Adder / Subtractor (program an array of full adders) 5. Keyboard Input Examples: how to program for keyboard input. 6. The keyboard input asks for two numbers X and Y. Each ranges from 0 to 15 (by entering '00'to '15'). Afterward, a plus or minus sign ('+' or '-') should be entered to perform either an addition or subtraction. 7. To copy the demo executable and run it: atoz[193]% cp -p ~changw/html/205/prg/3/demo-a.out . atoz[194]% demo-a.out Enter X (range 00 ~ 15): 10 Enter Y (range 00 ~ 15): 03 Enter '+' or '-': + X=01010 (10) Y=00011 ( 3) C0=0 Result=01101 (+13) E = 0 atoz[195]% demo-a.out Enter X (range 00 ~ 15): 12 Enter Y (range 00 ~ 15): 13 Enter '+' or '-': https://athena.ecs.csus.edu/~changw/205/prg/3/KeyinExample 30/10/2019 https://athena.ecs.csus.edu/~changw/205/prg/3/ https://athena.ecs.csus.edu/~changw/205/prg/3/ 2/3 - X=01100 (12) Y=01101 (13) C0=1 Result=11111 (- 1) E = 0 atoz[196]% demo-a.out Enter X (range 00 ~ 15): 01 Enter Y (range 00 ~ 15): 15 Enter '+' or '-': - X=00001 ( 1) Y=01111 (15) C0=1 Result=10010 (-14) E = 0 atoz[197]% demo-a.out Enter X (range 00 ~ 15): 11 Enter Y (range 00 ~ 15): 15 Enter '+' or '-': + X=01011 (11) Y=01111 (15) C0=0 Result=11010 (- 6) E = 1 8. The ASCII value obtained from the input must be converted, e.g., if '13' is entered, it gets 49 and 51 (ASCII value), then a subtraction of 48 is needed for each to get the value of 10's and 1's. 9. The xor of the last two carries generates the E indicater. If E is 0, the sum bits are OK as a 2's complement result. If E is 1, then the final carry-out bit is needed to place in front of the result. Otherwise, the result will not be correct in the signed 2's complement bitmap. E is the true overflow indicator. overflowed.) 10. The skeleton of your program should look like this: // add-sub.v, 205 Verilog Programming Assignment #3 // can do both add & subtract on 5-bit operands // use arrays of gates and modules // // PUT YOUR NAME HERE module TestMod; parameter PLUS_SIGN = 43; parameter MINUS_SIGN = 45; parameter STDIN = 32'h8000_0000; // keyboard input channel reg [7:0] str [1:3]; // typing in, 3 chars reg [4:0] X, Y; // 5-bit X, Y to sum reg C0; // set 0/1 to do add/subtract wire [4:0] S; // 5-bit Sum to see as result wire E; // Error indicator, overflow instantiate AddSubMod (with input C0, X, and Y, output E and S) initial begin 1. prompt for keyboard entry --> $display("Enter X (range 00~15): "); get 1st character --> str[1] = $fgetc(STDIN); get 2nd character get 3rd character (Enter key) convert from 1st (10's) and 2nd (1's) chars to X 2. (repeat above for Y) 3. get a char (and the Enter key) if it is '+,' set C0 to 0 // add X and Y otherwise (assume '-'), set C0 to 1 // subtract Y from X 4. #2; // wait a bit for the add/sub to get done 5. display X, Y, S, and E (see demo runs) end endmodule 30/10/2019 https://athena.ecs.csus.edu/~changw/205/prg/3/ https://athena.ecs.csus.edu/~changw/205/prg/3/ 3/3 module AddSubMod(C0, X, Y, S, E); input C0; // single bit input input [4:0] X, Y, ... // 4-bit input items output ... output ... (multiple output lines due to size differences) ... ... use ARRAY of gates: xor my5xor [4:0] (...); and ARRAY of module instances: FullAdderMod my5FA [?:?] (...); endmodule module FullAdderMod(...); // single-bit adder module ... ... (follow the diagram) ... endmodule A List of Useful Linux and vi Commands Access Dropbox from a Linux Shell https://athena.ecs.csus.edu/~changw/class_docs/UnixVi.html https://athena.ecs.csus.edu/~changw/class_docs/AccessDropbox.html
Answered Same DayNov 01, 2021

Answer To: 30/10/2019 https://athena.ecs.csus.edu/~changw/205/prg/3/...

Gaurav answered on Nov 04 2021
154 Votes
result/a.out
#! /usr/share/iverilog-0.9.7/bin/vvp
:ivl_version "0.9.7 " "(v0_9_6)";
:vpi_time_precision + 0;
:vpi_module "system";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0x1b514e0 .scope module, "TestMod" "TestMod" 2 8;
.timescale 0 0;
P_0x1b53ae8 .param/l "MINUS_SIGN" 2 10, +C4<0101101>;
P_0x1b53b10 .param/l "PLUS_SIGN" 2 9, +C4<0101011>;
P_0x1b53b38 .param/l "STDIN" 2 11, C4<10000000000000000000000000000000>;
v0x1b7c660_0 .var "C0",
0 0;
v0x1b7c700_0 .net "E", 0 0, L_0x1b7d080; 1 drivers
v0x1b7c7b0_0 .net "S", 4 0, L_0x1b80e30; 1 drivers
v0x1b7c860_0 .var "X", 4 0;
v0x1b7c940_0 .var "Y", 4 0;
v0x1b7c9f0 .array "str", 3 1, 7 0;
S_0x1b515d0 .scope module, "dut" "AddSubMod" 2 17, 3 15, S_0x1b514e0;
.timescale 0 0;
L_0x1b795a0 .functor XOR 5, v0x1b7c940_0, L_0x1b7cc80, C4<00000>, C4<00000>;
L_0x1b7d080 .functor XOR 1, L_0x1b80d90, L_0x1b81070, C4<0>, C4<0>;
v0x1b7be70_0 .net "C0", 0 0, v0x1b7c660_0; 1 drivers
v0x1b7bf30_0 .net "Ciripple", 4 0, L_0x1b7cb10; 1 drivers
v0x1b7bfd0_0 .net "Coripple", 4 0, L_0x1b7d3d0; 1 drivers
v0x1b7c070_0 .alias "E", 0 0, v0x1b7c700_0;
v0x1b7c0f0_0 .alias "S", 4 0, v0x1b7c7b0_0;
v0x1b7c190_0 .net "X", 4 0, v0x1b7c860_0; 1 drivers
v0x1b7c230_0 .net "Y", 4 0, v0x1b7c940_0; 1 drivers
v0x1b7c2d0_0 .net "Yxor", 4 0, L_0x1b795a0; 1 drivers
v0x1b7c370_0 .net *"_s0", 5 0, L_0x1b7ca70; 1 drivers
v0x1b7c410_0 .net *"_s24", 0 0, L_0x1b80d90; 1 drivers
v0x1b7c4b0_0 .net *"_s26", 0 0, L_0x1b81070; 1 drivers
v0x1b7c550_0 .net *"_s4", 4 0, L_0x1b7cc80; 1 drivers
L_0x1b7ca70 .concat [ 1 5 0 0], v0x1b7c660_0, L_0x1b7d3d0;
L_0x1b7cb10 .part L_0x1b7ca70, 0, 5;
LS_0x1b7cc80_0_0 .concat [ 1 1 1 1], v0x1b7c660_0, v0x1b7c660_0, v0x1b7c660_0, v0x1b7c660_0;
LS_0x1b7cc80_0_4 .concat [ 1 0 0 0], v0x1b7c660_0;
L_0x1b7cc80 .concat [ 4 1 0 0], LS_0x1b7cc80_0_0, LS_0x1b7cc80_0_4;
L_0x1b7fc80 .part v0x1b7c860_0, 0, 1;
L_0x1b7fdc0 .part v0x1b7c860_0, 1, 1;
L_0x1b7feb0 .part v0x1b7c860_0, 2, 1;
L_0x1b80070 .part v0x1b7c860_0, 3, 1;
L_0x1b80110 .part v0x1b7c860_0, 4, 1;
L_0x1b80250 .part L_0x1b795a0, 0, 1;
L_0x1b80390 .part L_0x1b795a0, 1, 1;
L_0x1b80480 .part L_0x1b795a0, 2, 1;
L_0x1b805b0 .part L_0x1b795a0, 3, 1;
L_0x1b80650 .part L_0x1b795a0, 4, 1;
L_0x1b80740 .part L_0x1b7cb10, 0, 1;
L_0x1b80900 .part L_0x1b7cb10, 1, 1;
L_0x1b809f0 .part L_0x1b7cb10, 2, 1;
L_0x1b80c00 .part L_0x1b7cb10, 3, 1;
L_0x1b80ca0 .part L_0x1b7cb10, 4, 1;
LS_0x1b80e30_0_0 .concat [ 1 1 1 1], L_0x1b7cf10, L_0x1b7d890, L_0x1b7e1d0, L_0x1b7ea80;
LS_0x1b80e30_0_4 .concat [ 1 0 0 0], L_0x1b7f3d0;
L_0x1b80e30 .concat [ 4 1 0 0], LS_0x1b80e30_0_0, LS_0x1b80e30_0_4;
LS_0x1b7d3d0_0_0 .concat [ 1 1 1 1], L_0x1b7ce40, L_0x1b7d7f0, L_0x1b7e130, L_0x1b7e9e0;
LS_0x1b7d3d0_0_4 .concat [ 1 0 0 0], L_0x1b7f330;
L_0x1b7d3d0 .concat [ 4 1 0 0], LS_0x1b7d3d0_0_0, LS_0x1b7d3d0_0_4;
L_0x1b80d90 .part L_0x1b7d3d0, 3, 1;
L_0x1b81070 .part L_0x1b7d3d0, 4, 1;
S_0x1b7b4f0 .scope module, "my5FA[0]" "FullAdderMod" 3 30, 3 2, S_0x1b515d0;
.timescale 0 0;
v0x1b7b5e0_0 .net "A", 0 0, L_0x1b7fc80; 1 drivers
v0x1b7b6a0_0 .net "B", 0 0, L_0x1b80250; 1 drivers
v0x1b7b740_0 .net "Cin", 0 0, L_0x1b80740; 1 drivers
v0x1b7b7e0_0 .net "Cout", 0 0, L_0x1b7ce40; 1 drivers
v0x1b7b860_0 .net "Sum", 0 0, L_0x1b7cf10; 1 drivers
v0x1b7b900_0 .net *"_s10", 0 0, C4<0>; 1 drivers
v0x1b7b9a0_0 .net *"_s11", 1 0, L_0x1b7d330; 1 drivers
v0x1b7ba40_0 .net *"_s13", 1 0, L_0x1b7d540; 1 drivers
v0x1b7bae0_0 .net *"_s16", 0 0, C4<0>; 1 drivers
v0x1b7bb80_0 .net *"_s17", 1 0, L_0x1b7d6b0; 1 drivers
v0x1b7bc20_0 .net *"_s3", 1 0, L_0x1b7cfe0; 1 drivers
v0x1b7bcc0_0 .net *"_s6", 0 0, C4<0>; 1 drivers
v0x1b7bdd0_0 .net *"_s7", 1 0, L_0x1b7d170; 1 drivers
L_0x1b7ce40 .part L_0x1b7d6b0, 1, 1;
L_0x1b7cf10 .part L_0x1b7d6b0, 0, 1;
L_0x1b7cfe0 .concat [ 1 1 0 0], L_0x1b80740, C4<0>;
L_0x1b7d170 .concat [ 1 1 0 0], L_0x1b7fc80, C4<0>;
L_0x1b7d330 .arith/sum 2, L_0x1b7cfe0, L_0x1b7d170;
L_0x1b7d540 .concat [ 1 1 0 0], L_0x1b80250, C4<0>;
L_0x1b7d6b0 .arith/sum 2, L_0x1b7d330, L_0x1b7d540;
S_0x1b7ab70 .scope module, "my5FA[1]" "FullAdderMod" 3 30, 3 2, S_0x1b515d0;
.timescale 0 0;
v0x1b7ac60_0 .net "A", 0 0, L_0x1b7fdc0; 1 drivers
v0x1b7ad20_0 .net "B", 0 0, L_0x1b80390; 1 drivers
v0x1b7adc0_0 .net "Cin", 0 0, L_0x1b80900; 1 drivers
v0x1b7ae60_0 .net "Cout", 0 0, L_0x1b7d7f0; 1 drivers
v0x1b7aee0_0 .net "Sum", 0 0, L_0x1b7d890; 1 drivers
v0x1b7af80_0 .net *"_s10", 0 0, C4<0>; 1 drivers
v0x1b7b020_0 .net *"_s11", 1 0, L_0x1b7dca0; 1 drivers
v0x1b7b0c0_0 .net *"_s13", 1 0, L_0x1b7de40; 1 drivers
v0x1b7b160_0 .net *"_s16", 0 0, C4<0>; 1...
SOLUTION.PDF

Answer To This Question Is Available To Download

Related Questions & Answers

More Questions »

Submit New Assignment

Copy and Paste Your Assignment Here