Write a hierarchical gate-level HDL model of the multiplexer described in Problem 4.31. Problem 4.31 Construct a 16  1 multiplexer with two 8  1 and one 2  1 multiplexers. Use block diagrams. (HDL—see...

Write a hierarchical gate-level HDL model of the multiplexer described in Problem 4.31.

Problem 4.31

Construct a 16
 1 multiplexer with two 8
 1 and one 2
 1 multiplexers. Use block diagrams. (HDL—see Problem 4.65)

Problem 4.65

Write a hierarchical gate-level HDL model of the multiplexer described in Problem 4.31.