With regard to Figure 7.11 and exercise 17, we have not provided for any type of error handling, such as if the address on the address lines were invalid, or the memory couldn’t be read because of a...

With regard to Figure 7.11 and exercise 17, we have not provided for any type of error handling, such as if the address on the address lines were invalid, or the memory couldn’t be read because of a hardware error. What could we do with our bus model to provide for such events?