What would be the clock period of a pipelined MIPS architecture with two stages, one comprising Instruction Fetch, Instruction Decode and Execute, the other one Memory and Write Back? Assume Memory...

What would be the clock period of a pipelined MIPS architecture with two stages, one comprising Instruction Fetch, Instruction Decode and Execute, the other one Memory and Write Back? Assume Memory and ALU take 2ns while Registers and other logic take Ins or less.