What is the most significant disadvantage of a single data route design? Multiple Multiplexors are required. The clock period is determined by the longest delay. The JUMP instruction is not supported....

What is the most significant disadvantage of a single data route design?

Multiple Multiplexors are required.

The clock period is determined by the longest delay.

The JUMP instruction is not supported.

At any one moment, each datapath element can only perform one function.