We wish to design a SC pair of the type of so that when driven with vI 1 5 (0.2 V) cos t and vI2 5 0 it produces the largest possible output signal under the constraint that neither FET ever leave the...

We wish to design a SC pair of the type of so that when driven with vI 1 5 (0.2 V) cos t and vI2 5 0 it produces the largest possible output signal under the constraint that neither FET ever leave the saturation region. The available components are VDD 5 2VSS 5 5 V and RD1 5 RD2 5 10 kV, and the FETs have k9 5 100 A/V2 , Vt 5 0.4 V, 5 0, and 5 0. (a) Assuming RSS 5 `, and supposing we wish to satisfy Eq. (4.94) by an order of magnitude, or 4VOV 5 10 3 (0.2 V), what is the required ISS? What are the required WyL ratios for the FETs? Hint: increasing ISS to raise a will also lower VO1 and VO2 and bring the FETs closer to saturation. The most critical instants are when vo1 and vo2 reach their negative peaks. (b) What is the ensuing gain a? What are the total signals (sum of dc and ac components) vO1, vO2, and vOD?