Use the long-channel CMOS process and the topology seen in Fig. 23.6 to design a voltage reference of 3 VTHN. Simulate your design and show the VDD sensitivity and temperature behavior of the...

Use the long-channel CMOS process and the topology seen in Fig. 23.6 to design a voltage reference of 3 VTHN. Simulate your design and show the VDD sensitivity and temperature behavior of the reference. Do TCs of R₁
and R₂
affect the performance of the reference? Why or why not?

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Suppose it was desired, in Fig. 23.7 (see also Fig. 20.22), to make Ml and M2 the same size. However, to increase the gate source voltage of Ml, relative to M2, the width of M3 is increased by K. How do the equations governing the operation of the BMR change? How does the current flowing in the BMR change?