Use Espresso to minimize the truth tables for the FSD in Fig. 5.7 and draw the minimized circuit. Is your solution the same as that shown in Fig. 5.8? Determine the minimum clock period for the...

Use Espresso to minimize the truth tables for the FSD in Fig. 5.7 and draw the minimized circuit. Is your solution the same as that shown in Fig. 5.8? Determine the minimum clock period for the bit-serial multifunction register given in Fig. 5.9 where tst and tcq are each assumed to be 0.1 ns and delay for NOT and NAND gates are each 0.1 ns.