Digital Logic...

This is an Undergraduate DIGITAL LOGIC CLASS. Please use appropriate topics listed in the problems. I will attach two zip files. one file will have all the problems, that file will have all problems and a last problem 33. I will attach another file which is useful to solve 3.24. Solve all problems and draw all required diagrams on paper , but do not use some software to draw diagrams. please donot copy any answers from chegg, or any other sources.


Digital Logic Hw-2 https://v3.camscanner.com/user/download https://v3.camscanner.com/user/download https://v3.camscanner.com/user/download https://v3.camscanner.com/user/download https://v3.camscanner.com/user/download https://v3.camscanner.com/user/download https://v3.camscanner.com/user/download https://v3.camscanner.com/user/download https://v3.camscanner.com/user/download https://v3.camscanner.com/user/download it Exercise 3.33 Ben Bitdiddle has designed the circuit in Figure 3.74 to compute a registered four-input XOR function. Each two-input XOR gate has a propagation delay of 100 ps and a contamination delay of 55 ps. Each flip-flop has a setup time of 60 ps, a hold time of 20 ps, a clock-to-Q maximum delay of 70 ps, and a clock-to-Q minimum delay of 50 ps. (a) If there is no clock skew, what is the maximum operating frequency of the circuit? (b) How much clock skew can the circuit tolerate if it must operate at 2 GHz? (c) How much clock skew can the circuit tolerate before it might experience a hold time violation? (d) Alyssa P. Hacker points out that she can redesign the combinational logic between the registers to be faster and tolerate more clock skew. Her improved circuit also uses three two-input XORs, but they are arranged differently. What is her circuit? What is its maximum frequency if there is no clock skew? How much clock skew can the circuit tolerate before it might experience a hold time violation? CLK lc CLK