This is a level-sensitive latch since the state of the output is dependent on the level of the clock signal. Figure 1: Figure for one of the questions. Ore te live CLK D CIL Figure 2: Figure for one...

please also draw the line for clock signal.


Extracted text: This is a level-sensitive latch since the state of the output is dependent on the level of the clock signal. Figure 1: Figure for one of the questions. Ore te live CLK D CIL Figure 2: Figure for one of the questions.


Extracted text: Referring to figures the resulting auPut at Q? Please explain 1 and2, what is Note: -Q is the same thing as Q' D --Q CLK = 1 When CLK = 1, the select line of the left-most tri-state buffer is 1, and the select line of the other tri-state buffer is 0. Thus, the value of D' appears at -Q, while the value (D')' appears at Q. CLK Positive-level-sensitive D latch -Q CLK = 0 closed switch (connection) connection Tri-state buffer When CLK-0, the select inputs are opposite from above. So the value of D does not matter, since it is not connected. The OLD value of D, however, is fed back to the circuit. оpen switch (no connection) inverter Copyright Michael Weeks 2004, 2014 This is a level-sensitive latch since the state of the output is dependent on the level of the clock signal.