This code warrior assignment will involve assembly language and C programming. Use the tutorial file to correctly format the code warrior. The shell to write also put the lecture and tips in the files...

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This code warrior assignment will involve assembly language and C programming. Use the tutorial file to correctly format the code warrior. The shell to write also put the lecture and tips in the files to help. You cant use Brset in the code. I provided tips and lectures to assist with the assignment. Let me know If the tutor would like my online information to access the lecture video.


Important:


I'll need the program files, screenshots of the code, debugger screenshot and a picture of the board working with my name on a piece of paper next to the board.




1 CodeWarrior Tutorial For C Programming Part I: How to Create a C Project 1. Open the CodeWarrior IDE: 2. Click the button “Create New Project”; 3. If the CodeWarrior is already open, and you see following window: Then, click File->New Project; 2 4. The new project Wizard window is open, choose the correct microcontroller chip in the “Select the derivative you would like to use” box: please choose MC9S12DG256B 5. In the “Choose your default connection” box, choose “Full Chip Simulation”, then click next 6. In the new window,check the box for C programming if it is not checked: 3 7. In the “Project name” box, type your project name, for example, Tutorial_C.mcp, and click the “Set…” button to choose a folder for your project: 8. Please create a folder called EET430L on your H drive or your flash drive. Then, come back to CodeWarrior to choose this folder in your H drive or your flash drive. After choosing the folder, click “Save”. Then, click “Next”. 4 9. You don’t need to do anything in the floowing window, just click “Next”: 10. In the next window, check the button labeled “None”, then, click “Next”: 11. In the following window, choose the followings: Minimal startup code Small None Then, clock “Next” 5 12. In the following window, choose “No” for PC-lint(PM): 13. Then, click “Finish”, and this is what you will see: 6 14. Double click the main.c to expand the main.c window: 15. Use mouse to high light everything in the main.c window, then, backspace to delete everything: 7 16. Download the text file called “CodeWarrior C Program Shell.txt” (located on the next page in Unit 1). Use Notepad to open it, copy everything in it, and paste to the main.c window: 17. Save your project by clicking the disk icon at the top left. At this point, you have created a new project called Tutorial_C with a working C program consisting of main.c, subroutine InitSwitches(), InitLEDs(), and DelayTime(). Part II: How to Compile and Test Your program 1. Click the “Make” button as shown: 8 2. The C compiler will open a box to show the errors if compilation is not successful; 3. Fix all errors, save the file, then, compile again. 4. After a successful compilation, you can test your program using the simulator and its Data window, Regsiter window, and Memory window. 5. To test your program using a Dragon12-Light board, you must change the setting from “Full Chip Simulation” to “HCS12 Serial Monitor” as shown: 6. After changing to “HCS12 Serial Monitor”, complie again: 9 7. To download and test your program, click the “Debug” button, the “True-Time Simulator & Real-Time Debugger” window will open. Click the “Start/Continue” button, flip some DIP switches high/low, and see the corresponding LEDs are turn on/off. Note: For CodeWarrior to function properly, your main.c should always have an infinite loop at the end. In the example above, we used a forever for-loop to read from DIP switches, and turn on/off the LEDs continously. If your man.c does not need to do some thing forever, after everything is done, add an infinite loop at the end of the main(): For(; ;) { } /*stay here forever*/ or ;File Name: ;Date: ;Purpose: ;Procedure: ; ; ;Test: ; ; ;***************************************************************** ;export symbols ;***************************************************************** ;For absolute assembly: this is the application entry point ABSENTRY Main ;***************************************************************** ; Include derivative-specific definitions ;***************************************************************** ;The microcontroller chip used by Dragon12-plus2 board INCLUDE 'mc9s12dg256.inc' ;***************************************************************** ;Symbolic constant(EQU) section ;***************************************************************** DATA EQU RAMStart ;use $1000 - $1FFF for data STACK EQU RAMEnd+1 ;use $2000 - $3FFF for stack CODE EQU $4000 ;use flash ROM $4000 - $7FFF for code ;***************************************************************** ; Data section ;***************************************************************** ORG DATA ;***************************************************************** ; Main program section ;***************************************************************** ORG CODE Main: LDS #STACK Repeat LDAA #$5A ;A = $5A LDAB#$12 ;B = $12 ABA ;Do A + B, the sume is in A: A = $6C STAA $1050 ;save the sunm to RAM location $1050 BRA Repeat ;repeat this process forever ;***************************************************************** ; Subroutine section ;***************************************************************** ;***************************************************************** ; Interrupt Vectors ;***************************************************************** ORG $FFFE DC.W Main ;Reset Vector
Answered Same DayMay 14, 2021

Answer To: This code warrior assignment will involve assembly language and C programming. Use the tutorial file...

Gaurav answered on May 18 2021
151 Votes
dip_switch_c/bin/Project.abs
dip_switch_c/bin/Project.abs.phy
S0370000443A5C436F646557617272696F722050726F6A656374735C6469705F7377697463685F635C62696E5C50726F6A6563742E616273AB
S2240FC000FEC033FDC031270E35ED31EC3169700434FB310326F2FEC035EC31270BED3118B8
S2240FC0200A30700434F920F13DCF090007D206C03B0000C037C0750000000010EF7900026B
S2240FC040C6FF5B03790262202AC6555B3F585B3F4F000105790001201A1F0260810686FF45
S21B0FC0605A0120E51F026001035420051F026001D85B0120D40000AD
S2060FFFFEC02904
S9030000FC
dip_switch_c/bin/Project.abs.s19
S0370000443A5C436F646557617272696F722050726F6A656374735C6469705F7377697463685F635C62696E5C50726F6A6563742E616273AB
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S123C0200A30700434F920F13DCF090007D206C03B0000C037C0750000000010EF7900027B
S123C040C6FF5B03790262202AC6555B3F585B3F4F000105790001201A1F0260810686FF55
S11AC0605A0120E51F026001035420051F026001D85B0120D40000BD
S105FFFEC02914
S9030000FC
dip_switch_c/bin/Project.map
*** EVALUATION ***
PROGRAM "D:\CodeWarrior Projects\dip_switch_c\bin\Project.abs"
*********************************************************************************************
TARGET SECTION
---------------------------------------------------------------------------------------------
Processor : Freescale HC12
Memory Model: SMALL
File Format : ELF\DWARF 2.0
Linker : SmartLinker V-5.0.52 Build 15249, Sep 7 2015
*********************************************************************************************
FILE SECTION
---------------------------------------------------------------------------------------------
mc9s12c32.c.o Model: SMALL, Lang: ANSI-C, Compiler Version: ANSI-C/cC++ Compiler for HC12 V-5.0.46 Build 15249, Sep 7 2015
main.c.o Model: SMALL, Lang: ANSI-C, Compiler Version: ANSI-C/cC++ Compiler for HC12 V-5.0.46 Build 15249, Sep 7 2015
Start12.c.o Model: SMALL, Lang: ANSI-C, Compiler Version: ANSI-C/cC++ Compiler for HC12 V-5.0.46 Build 15249, Sep 7 2015
*********************************************************************************************
STARTUP SECTION
---------------------------------------------------------------------------------------------
Entry point: 0xC029 (_Startup)
_startupData is allocated at 0xC031 and uses 6 Bytes
extern struct _tagStartup {
unsigned nofZeroOut 0
_Copy *toCopyDownBeg 0xC075
} _startupData;
*********************************************************************************************
SECTION-ALLOCATION SECTION
Section Name Size Type From To Segment
---------------------------------------------------------------------------------------------
.init 49 R 0xC000 0xC030 ROM_C000
.startData 10 R 0xC031 0xC03A ROM_C000
.text 58 R 0xC03B 0xC074 ROM_C000
.copy 2 R 0xC075 0xC076 ROM_C000
.stack 256 R/W 0x800 0x8FF RAM
.abs_section_8 1 N/I 0x8 0x8 .absSeg0
.abs_section_9 1 N/I 0x9 0x9 .absSeg1
.abs_section_a 1 N/I 0xA 0xA .absSeg2
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.abs_section_c 1 N/I 0xC 0xC .absSeg4
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.abs_section_ca 1 N/I 0xCA 0xCA .absSeg56
.abs_section_cb 1 N/I 0xCB 0xCB .absSeg57
.abs_section_cc 1 N/I 0xCC 0xCC .absSeg58
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.abs_section_db 1 N/I 0xDB 0xDB .absSeg65
.abs_section_dd 1 N/I 0xDD 0xDD .absSeg66
.abs_section_e0 1 N/I 0xE0 0xE0 .absSeg67
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.abs_
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.abs_section_ec 2 N/I 0xEC 0xED .absSeg210
.abs_section_ee 2 N/I 0xEE 0xEF .absSeg211
.abs_section_f0 2 N/I 0xF0 0xF1 .absSeg212
.abs_section_f2 2 N/I 0xF2 0xF3 .absSeg213
.abs_section_f4 2 N/I 0xF4 0xF5 .absSeg214
.abs_section_f6 2 N/I 0xF6 0xF7 .absSeg215
.abs_section_f8 2 N/I 0xF8 0xF9 .absSeg216
.abs_section_fa 2 N/I 0xFA 0xFB .absSeg217
.abs_section_fc 2 N/I 0xFC 0xFD .absSeg218
.abs_section_16e 2 N/I 0x16E 0x16F .absSeg219
.abs_section_17e 2 N/I 0x17E 0x17F .absSeg220
.vectSeg221_vect 2 R 0xFFFE 0xFFFF .vectSeg221
Summary of section sizes per section type:
READ_ONLY (R): 79 (dec: 121)
READ_WRITE (R/W): 100 (dec: 256)
NO_INIT (N/I): 104 (dec: 260)
*********************************************************************************************
VECTOR-ALLOCATION SECTION
Address InitValue InitFunction
---------------------------------------------------------------------------------------------
0xFFFE 0xC029 _Startup
*********************************************************************************************
OBJECT-ALLOCATION SECTION
Name Module Addr hSize dSize Ref Section RLIB
---------------------------------------------------------------------------------------------
MODULE: -- mc9s12c32.c.o --
- PROCEDURES:
- VARIABLES:
_PORTE 8 1 1 0 .abs_section_8
_DDRE 9 1 1 0 .abs_section_9
_PEAR A 1 1 0 .abs_section_a
_MODE B 1 1 0 .abs_section_b
_PUCR C 1 1 0 .abs_section_c
_RDRIV D 1 1 0 .abs_section_d
_EBICTL E 1 1 0 .abs_section_e
_INITRM 10 1 1 0 .abs_section_10
_INITRG 11 1 1 0 .abs_section_11
_MISC 13 1 1 0 .abs_section_13
_ITCR 15 1 1 0 .abs_section_15
_ITEST 16 1 1 0 .abs_section_16
_VREGCTRL 19 1 1 0 .abs_section_19
_MEMSIZ0 1C 1 1 0 .abs_section_1c
_MEMSIZ1 1D 1 1 0 .abs_section_1d
_INTCR 1E 1 1 0 .abs_section_1e
_HPRIO 1F 1 1 0 .abs_section_1f
_DBGC1 20 1 1 0 .abs_section_20
_DBGSC 21 1 1 0 .abs_section_21
_DBGCNT 24 1 1 0 .abs_section_24
_DBGCCX 25 1 1 0 .abs_section_25
_DBGC2 28 1 1 0 .abs_section_28
_DBGC3 29 1 1 0 .abs_section_29
_DBGCAX 2A 1 1 0 .abs_section_2a
_DBGCBX 2D 1 1 0 .abs_section_2d
_PPAGE 30 1 1 0 .abs_section_30
_SYNR 34 1 1 0 .abs_section_34
_REFDV 35 1 1 0 .abs_section_35
_CRGFLG 37 1 1 0 .abs_section_37
_CRGINT 38 1 1 0 .abs_section_38
_CLKSEL 39 1 1 0 .abs_section_39
_PLLCTL 3A 1 1 0 .abs_section_3a
_RTICTL 3B 1 1 0 .abs_section_3b
_COPCTL 3C 1 1 0 .abs_section_3c
_ARMCOP 3F 1 1 0 .abs_section_3f
_TIOS 40 1 1 0 .abs_section_40
_CFORC 41 1 1 0 .abs_section_41
_OC7M 42 1 1 0 .abs_section_42
_OC7D 43 1 1 0 .abs_section_43
_TSCR1 46 1 1 0 .abs_section_46
_TTOV 47 1 1 0 .abs_section_47
_TCTL1 48 1 1 0 .abs_section_48
_TCTL2 49 1 1 0 .abs_section_49
_TCTL3 4A 1 1 0 .abs_section_4a
_TCTL4 4B 1 1 0 .abs_section_4b
_TIE 4C 1 1 0 .abs_section_4c
_TSCR2 4D 1 1 0 .abs_section_4d
_TFLG1 4E 1 1 0 .abs_section_4e
_TFLG2 4F 1 1 0 .abs_section_4f
_PACTL 60 1 1 0 .abs_section_60
_PAFLG 61 1 1 0 .abs_section_61
_ATDSTAT0 86 1 1 0 .abs_section_86
_ATDTEST1 89 1 1 0 .abs_section_89
_ATDSTAT1 8B 1 1 0 .abs_section_8b
_ATDDIEN 8D 1 1 0 .abs_section_8d
_PORTAD0 8F 1 1 0 .abs_section_8f
_SCICR1 CA 1 1 0 .abs_section_ca
_SCICR2 CB 1 1 0 .abs_section_cb
_SCISR1 CC 1 1 0 .abs_section_cc
_SCISR2 CD 1 1 0 .abs_section_cd
_SCIDRH CE 1 1 0 .abs_section_ce
_SCIDRL CF 1 1 0 .abs_section_cf
_SPICR1 D8 1 1 0 .abs_section_d8
_SPICR2 D9 1 1 0 .abs_section_d9
_SPIBR DA 1 1 0 .abs_section_da
_SPISR DB 1 1 0 .abs_section_db
_SPIDR DD 1 1 0 .abs_section_dd
_PWME E0 1 1 0 .abs_section_e0
_PWMPOL E1 1 1 0 .abs_section_e1
_PWMCLK E2 1 1 0 .abs_section_e2
_PWMPRCLK E3 1 1 0 .abs_section_e3
_PWMCAE E4 1 1 0 .abs_section_e4
_PWMCTL E5 1 1 0 .abs_section_e5
_PWMSCLA E8 1 1 0 .abs_section_e8
_PWMSCLB E9 1 1 0 .abs_section_e9
_PWMSDN FE 1 1 0 .abs_section_fe
_FCLKDIV 100 1 1 0 .abs_section_100
_FSEC 101 1 1 0 .abs_section_101
_FCNFG 103 1 1 0 .abs_section_103
_FPROT 104 1 1 0 .abs_section_104
_FSTAT 105 1 1 0 .abs_section_105
_FCMD 106 1 1 0 .abs_section_106
_CANCTL0 140 1 1 0 .abs_section_140
_CANCTL1 141 1 1 0 .abs_section_141
_CANBTR0 142 1 1 0 .abs_section_142
_CANBTR1 143 1 1 0 .abs_section_143
_CANRFLG 144 1 1 0 .abs_section_144
_CANRIER 145 1 1 0 .abs_section_145
_CANTFLG 146 1 1 0 .abs_section_146
_CANTIER 147 1 1 0 .abs_section_147
_CANTARQ 148 1 1 0 .abs_section_148
_CANTAAK 149 1 1 0 .abs_section_149
_CANTBSEL 14A 1 1 0 .abs_section_14a
_CANIDAC 14B 1 1 0 .abs_section_14b
_CANRXERR 14E 1 1 0 .abs_section_14e
_CANTXERR 14F 1 1 0 .abs_section_14f
_CANIDAR0 150 1 1 0 .abs_section_150
_CANIDAR1 151 1 1 0 .abs_section_151
_CANIDAR2 152 1 1 0 .abs_section_152
_CANIDAR3 153 1 1 0 .abs_section_153
_CANIDMR0 154 1 1 0 .abs_section_154
_CANIDMR1 155 1 1 0 .abs_section_155
_CANIDMR2 156 1 1 0 .abs_section_156
_CANIDMR3 157 1 1 0 .abs_section_157
_CANIDAR4 158 1 1 0 .abs_section_158
_CANIDAR5 159 1 1 0 .abs_section_159
_CANIDAR6 15A 1 1 0 .abs_section_15a
_CANIDAR7 15B 1 1 0 .abs_section_15b
_CANIDMR4 15C 1 1 0 .abs_section_15c
_CANIDMR5 15D 1 1 0 .abs_section_15d
_CANIDMR6 15E 1 1 0 .abs_section_15e
_CANIDMR7 15F 1 1 0 .abs_section_15f
_CANRXIDR0 160 1 1 0 .abs_section_160
_CANRXIDR1 161 1 1 0 .abs_section_161
_CANRXIDR2 162 1 1 0 .abs_section_162
_CANRXIDR3 163 1 1 0 .abs_section_163
_CANRXDSR0 164 1 1 0 .abs_section_164
_CANRXDSR1 165 1 1 0 .abs_section_165
_CANRXDSR2 166 1 1 0 .abs_section_166
_CANRXDSR3 167 1 1 0 .abs_section_167
_CANRXDSR4 168 1 1 0 .abs_section_168
_CANRXDSR5 169 1 1 0 .abs_section_169
_CANRXDSR6 16A 1 1 0 .abs_section_16a
_CANRXDSR7 16B 1 1 0 .abs_section_16b
_CANRXDLR 16C 1 1 0 .abs_section_16c
_CANTXIDR0 170 1 1 0 .abs_section_170
_CANTXIDR1 171 1 1 0 .abs_section_171
_CANTXIDR2 172 1 1 0 .abs_section_172
_CANTXIDR3 173 1 1 0 .abs_section_173
_CANTXDSR0 174 1 1 0 .abs_section_174
_CANTXDSR1 175 1 1 0 .abs_section_175
_CANTXDSR2 176 1 1 0 .abs_section_176
_CANTXDSR3 177 1 1 0 .abs_section_177
_CANTXDSR4 178 1 1 0 .abs_section_178
_CANTXDSR5 179 1 1 0 .abs_section_179
_CANTXDSR6 17A 1 1 0 .abs_section_17a
_CANTXDSR7 17B 1 1 0 .abs_section_17b
_CANTXDLR 17C 1 1 0 .abs_section_17c
_CANTXTBPR 17D 1 1 0 .abs_section_17d
_PTT 240 1 1 0 .abs_section_240
_PTIT 241 1 1 0 .abs_section_241
_DDRT 242 1 1 0 .abs_section_242
_RDRT 243 1 1 0 .abs_section_243
_PERT 244 1 1 0 .abs_section_244
_PPST 245 1 1 0 .abs_section_245
_MODRR 247 1 1 0 .abs_section_247
_PTS 248 1 1 0 .abs_section_248
_PTIS 249 1 1 0 .abs_section_249
_DDRS 24A 1 1 0 .abs_section_24a
_RDRS 24B 1 1 0 .abs_section_24b
_PERS 24C 1 1 0 .abs_section_24c
_PPSS 24D 1 1 0 .abs_section_24d
_WOMS 24E 1 1 0 .abs_section_24e
_PTM 250 1 1 0 .abs_section_250
_PTIM 251 1 1 0 .abs_section_251
_DDRM 252 1 1 0 .abs_section_252
_RDRM 253 1 1 0 .abs_section_253
_PERM 254 1 1 0 .abs_section_254
_PPSM 255 1 1 0 .abs_section_255
_WOMM 256 1 1 0 .abs_section_256
_PTP 258 1 1 0 .abs_section_258
_PTIP 259 1 1 0 .abs_section_259
_DDRP 25A 1 1 0 .abs_section_25a
_RDRP 25B 1 1 0 .abs_section_25b
_PERP 25C 1 1 0 .abs_section_25c
_PPSP 25D 1 1 0 .abs_section_25d
_PIEP 25E 1 1 0 .abs_section_25e
_PIFP 25F 1 1 0 .abs_section_25f
_PTJ 268 1 1 0 .abs_section_268
_PTIJ 269 1 1 0 .abs_section_269
_DDRJ 26A 1 1 0 .abs_section_26a
_RDRJ 26B 1 1 0 .abs_section_26b
_PERJ 26C 1 1 0 .abs_section_26c
_PPSJ 26D 1 1 0 .abs_section_26d
_PIEJ 26E 1 1 0 .abs_section_26e
_PIFJ 26F 1 1 0 .abs_section_26f
_PTAD 270 1 1 0 .abs_section_270
_PTIAD 271 1 1 0 .abs_section_271
_DDRAD 272 1 1 0 .abs_section_272
_RDRAD 273 1 1 0 .abs_section_273
_PERAD 274 1 1 0 .abs_section_274
_PPSAD 275 1 1 0 .abs_section_275
_PORTAB 0 2 2 4 .abs_section_0
_DDRAB 2 2 2 2 .abs_section_2
_PARTID 1A 2 2 0 .abs_section_1a
_DBGTB 22 2 2 0 .abs_section_22
_DBGCC 26 2 2 0 .abs_section_26
_DBGCA 2B 2 2 0 .abs_section_2b
_DBGCB 2E 2 2 0 .abs_section_2e
_TCNT 44 2 2 0 .abs_section_44
_TC0 50 2 2 0 .abs_section_50
_TC1 52 2 2 0 .abs_section_52
_TC2 54 2 2 0 .abs_section_54
_TC3 56 2 2 0 .abs_section_56
_TC4 58 2 2 0 .abs_section_58
_TC5 5A 2 2 0 .abs_section_5a
_TC6 5C 2 2 0 .abs_section_5c
_TC7 5E 2 2 0 .abs_section_5e
_PACNT 62 2 2 0 .abs_section_62
_ATDCTL23 82 2 2 0 .abs_section_82
_ATDCTL45 84 2 2 0 .abs_section_84
_ATDDR0 90 2 2 0 .abs_section_90
_ATDDR1 92 2 2 0 .abs_section_92
_ATDDR2 94 2 2 0 .abs_section_94
_ATDDR3 96 2 2 0 .abs_section_96
_ATDDR4 98 2 2 0 .abs_section_98
_ATDDR5 9A 2 2 0 .abs_section_9a
_ATDDR6 9C 2 2 0 .abs_section_9c
_ATDDR7 9E 2 2 0 .abs_section_9e
_SCIBD C8 2 2 0 .abs_section_c8
_PWMCNT01 EC 2 2 0 .abs_section_ec
_PWMCNT23 EE 2 2 0 .abs_section_ee
_PWMCNT45 F0 2 2 0 .abs_section_f0
_PWMPER01 F2 2 2 0 .abs_section_f2
_PWMPER23 F4 2 2 0 .abs_section_f4
_PWMPER45 F6 2 2 0 .abs_section_f6
_PWMDTY01 F8 2 2 0 .abs_section_f8
_PWMDTY23 FA 2 2 0 .abs_section_fa
_PWMDTY45 FC 2 2 0 .abs_section_fc
_CANRXTSR 16E 2 2 0 .abs_section_16e
_CANTXTSR 17E 2 2 0 .abs_section_17e
MODULE: -- main.c.o --
- PROCEDURES:
main C03B 3A 58 1 .text
- VARIABLES:
MODULE: -- Start12.c.o --
- PROCEDURES:
Init C000 29 41 1 .init
_Startup C029 8 8 0 .init
- VARIABLES:
_startupData C031 6 6 3 .startData
- LABELS:
__SEG_END_SSTACK 900 0 0 1
*********************************************************************************************
MODULE STATISTIC
Name Data Code Const
---------------------------------------------------------------------------------------------
mc9s12c32.c.o 260 0 0
main.c.o 0 58 0
Start12.c.o 0 49 0
other 256 12 2
*********************************************************************************************
SECTION USE IN OBJECT-ALLOCATION SECTION
---------------------------------------------------------------------------------------------
SECTION: ".text"
main
SECTION: ".init"
Init _Startup
SECTION: ".abs_section_8"
_PORTE
SECTION: ".abs_section_9"
_DDRE
SECTION: ".abs_section_a"
_PEAR
SECTION: ".abs_section_b"
_MODE
SECTION: ".abs_section_c"
_PUCR
SECTION: ".abs_section_d"
_RDRIV
SECTION: ".abs_section_e"
_EBICTL
SECTION: ".abs_section_10"
_INITRM
SECTION: ".abs_section_11"
_INITRG
SECTION: ".abs_section_13"
_MISC
SECTION: ".abs_section_15"
_ITCR
SECTION: ".abs_section_16"
_ITEST
SECTION: ".abs_section_19"
_VREGCTRL
SECTION: ".abs_section_1c"
_MEMSIZ0
SECTION: ".abs_section_1d"
_MEMSIZ1
SECTION: ".abs_section_1e"
_INTCR
SECTION: ".abs_section_1f"
_HPRIO
SECTION: ".abs_section_20"
_DBGC1
SECTION: ".abs_section_21"
_DBGSC
SECTION: ".abs_section_24"
_DBGCNT
SECTION: ".abs_section_25"
_DBGCCX
SECTION: ".abs_section_28"
_DBGC2
SECTION: ".abs_section_29"
_DBGC3
SECTION: ".abs_section_2a"
_DBGCAX
SECTION: ".abs_section_2d"
_DBGCBX
SECTION: ".abs_section_30"
_PPAGE
SECTION: ".abs_section_34"
_SYNR
SECTION: ".abs_section_35"
_REFDV
SECTION: ".abs_section_37"
_CRGFLG
SECTION: ".abs_section_38"
_CRGINT
SECTION: ".abs_section_39"
_CLKSEL
SECTION: ".abs_section_3a"
_PLLCTL
SECTION: ".abs_section_3b"
_RTICTL
SECTION: ".abs_section_3c"
_COPCTL
SECTION: ".abs_section_3f"
_ARMCOP
SECTION: ".abs_section_40"
_TIOS
SECTION: ".abs_section_41"
_CFORC
SECTION: ".abs_section_42"
_OC7M
SECTION: ".abs_section_43"
_OC7D
SECTION: ".abs_section_46"
_TSCR1
SECTION: ".abs_section_47"
_TTOV
SECTION: ".abs_section_48"
_TCTL1
SECTION: ".abs_section_49"
_TCTL2
SECTION: ".abs_section_4a"
_TCTL3
SECTION: ".abs_section_4b"
_TCTL4
SECTION: ".abs_section_4c"
_TIE
SECTION: ".abs_section_4d"
_TSCR2
SECTION: ".abs_section_4e"
_TFLG1
SECTION: ".abs_section_4f"
_TFLG2
SECTION: ".abs_section_60"
_PACTL
SECTION: ".abs_section_61"
_PAFLG
SECTION: ".abs_section_86"
_ATDSTAT0
SECTION: ".abs_section_89"
_ATDTEST1
SECTION: ".abs_section_8b"
_ATDSTAT1
SECTION: ".abs_section_8d"
_ATDDIEN
SECTION: ".abs_section_8f"
_PORTAD0
SECTION: ".abs_section_ca"
_SCICR1
SECTION: ".abs_section_cb"
_SCICR2
SECTION: ".abs_section_cc"
_SCISR1
SECTION: ".abs_section_cd"
_SCISR2
SECTION: ".abs_section_ce"
_SCIDRH
SECTION: ".abs_section_cf"
_SCIDRL
SECTION: ".abs_section_d8"
_SPICR1
SECTION: ".abs_section_d9"
_SPICR2
SECTION: ".abs_section_da"
_SPIBR
SECTION: ".abs_section_db"
_SPISR
SECTION: ".abs_section_dd"
_SPIDR
SECTION: ".abs_section_e0"
_PWME
SECTION: ".abs_section_e1"
_PWMPOL
SECTION: ".abs_section_e2"
_PWMCLK
SECTION: ".abs_section_e3"
_PWMPRCLK
SECTION: ".abs_section_e4"
_PWMCAE
SECTION: ".abs_section_e5"
_PWMCTL
SECTION: ".abs_section_e8"
_PWMSCLA
SECTION: ".abs_section_e9"
_PWMSCLB
SECTION: ".abs_section_fe"
_PWMSDN
SECTION: ".abs_section_100"
_FCLKDIV
SECTION: ".abs_section_101"
_FSEC
SECTION: ".abs_section_103"
_FCNFG
SECTION: ".abs_section_104"
_FPROT
SECTION: ".abs_section_105"
_FSTAT
SECTION: ".abs_section_106"
_FCMD
SECTION: ".abs_section_140"
_CANCTL0
SECTION: ".abs_section_141"
_CANCTL1
SECTION: ".abs_section_142"
_CANBTR0
SECTION: ".abs_section_143"
_CANBTR1
SECTION: ".abs_section_144"
_CANRFLG
SECTION: ".abs_section_145"
_CANRIER
SECTION: ".abs_section_146"
_CANTFLG
SECTION: ".abs_section_147"
_CANTIER
SECTION: ".abs_section_148"
_CANTARQ
SECTION: ".abs_section_149"
_CANTAAK
SECTION: ".abs_section_14a"
_CANTBSEL
SECTION: ".abs_section_14b"
_CANIDAC
SECTION: ".abs_section_14e"
_CANRXERR
SECTION: ".abs_section_14f"
_CANTXERR
SECTION: ".abs_section_150"
_CANIDAR0
SECTION: ".abs_section_151"
_CANIDAR1
SECTION: ".abs_section_152"
_CANIDAR2
SECTION: ".abs_section_153"
_CANIDAR3
SECTION: ".abs_section_154"
_CANIDMR0
SECTION: ".abs_section_155"
_CANIDMR1
SECTION: ".abs_section_156"
_CANIDMR2
SECTION: ".abs_section_157"
_CANIDMR3
SECTION: ".abs_section_158"
_CANIDAR4
SECTION: ".abs_section_159"
_CANIDAR5
SECTION: ".abs_section_15a"
_CANIDAR6
SECTION: ".abs_section_15b"
_CANIDAR7
SECTION: ".abs_section_15c"
_CANIDMR4
SECTION: ".abs_section_15d"
_CANIDMR5
SECTION: ".abs_section_15e"
_CANIDMR6
SECTION: ".abs_section_15f"
_CANIDMR7
SECTION: ".abs_section_160"
_CANRXIDR0
SECTION: ".abs_section_161"
_CANRXIDR1
SECTION: ".abs_section_162"
_CANRXIDR2
SECTION: ".abs_section_163"
_CANRXIDR3
SECTION: ".abs_section_164"
_CANRXDSR0
SECTION: ".abs_section_165"
_CANRXDSR1
SECTION: ".abs_section_166"
_CANRXDSR2
SECTION: ".abs_section_167"
_CANRXDSR3
SECTION: ".abs_section_168"
_CANRXDSR4
SECTION: ".abs_section_169"
_CANRXDSR5
SECTION: ".abs_section_16a"
_CANRXDSR6
SECTION: ".abs_section_16b"
_CANRXDSR7
SECTION: ".abs_section_16c"
_CANRXDLR
SECTION: ".abs_section_170"
_CANTXIDR0
SECTION: ".abs_section_171"
_CANTXIDR1
SECTION: ".abs_section_172"
_CANTXIDR2
SECTION: ".abs_section_173"
_CANTXIDR3
SECTION: ".abs_section_174"
_CANTXDSR0
SECTION: ".abs_section_175"
_CANTXDSR1
SECTION: ".abs_section_176"
_CANTXDSR2
SECTION: ".abs_section_177"
_CANTXDSR3
SECTION: ".abs_section_178"
_CANTXDSR4
SECTION: ".abs_section_179"
_CANTXDSR5
SECTION: ".abs_section_17a"
_CANTXDSR6
SECTION: ".abs_section_17b"
_CANTXDSR7
SECTION: ".abs_section_17c"
_CANTXDLR
SECTION: ".abs_section_17d"
_CANTXTBPR
SECTION: ".abs_section_240"
_PTT
SECTION: ".abs_section_241"
_PTIT
SECTION: ".abs_section_242"
_DDRT
SECTION: ".abs_section_243"
_RDRT
SECTION: ".abs_section_244"
_PERT
SECTION: ".abs_section_245"
_PPST
SECTION: ".abs_section_247"
_MODRR
SECTION: ".abs_section_248"
_PTS
SECTION: ".abs_section_249"
_PTIS
SECTION: ".abs_section_24a"
_DDRS
SECTION: ".abs_section_24b"
_RDRS
SECTION: ".abs_section_24c"
_PERS
SECTION: ".abs_section_24d"
_PPSS
SECTION: ".abs_section_24e"
_WOMS
SECTION: ".abs_section_250"
_PTM
SECTION: ".abs_section_251"
_PTIM
SECTION: ".abs_section_252"
_DDRM
SECTION: ".abs_section_253"
_RDRM
SECTION: ".abs_section_254"
_PERM
SECTION: ".abs_section_255"
_PPSM
SECTION: ".abs_section_256"
_WOMM
SECTION: ".abs_section_258"
_PTP
SECTION: ".abs_section_259"
_PTIP
SECTION: ".abs_section_25a"
_DDRP
SECTION: ".abs_section_25b"
_RDRP
SECTION: ".abs_section_25c"
_PERP
SECTION: ".abs_section_25d"
_PPSP
SECTION: ".abs_section_25e"
_PIEP
SECTION: ".abs_section_25f"
_PIFP
SECTION: ".abs_section_268"
_PTJ
SECTION: ".abs_section_269"
_PTIJ
SECTION: ".abs_section_26a"
_DDRJ
SECTION: ".abs_section_26b"
_RDRJ
SECTION: ".abs_section_26c"
_PERJ
SECTION: ".abs_section_26d"
_PPSJ
SECTION: ".abs_section_26e"
_PIEJ
SECTION: ".abs_section_26f"
_PIFJ
SECTION: ".abs_section_270"
_PTAD
SECTION: ".abs_section_271"
_PTIAD
SECTION: ".abs_section_272"
_DDRAD
SECTION: ".abs_section_273"
_RDRAD
SECTION: ".abs_section_274"
_PERAD
SECTION: ".abs_section_275"
_PPSAD
SECTION: ".abs_section_0"
_PORTAB
SECTION: ".abs_section_2"
_DDRAB
SECTION: ".abs_section_1a"
_PARTID
SECTION: ".abs_section_22"
_DBGTB
SECTION: ".abs_section_26"
_DBGCC
SECTION: ".abs_section_2b"
_DBGCA
SECTION: ".abs_section_2e"
_DBGCB
SECTION: ".abs_section_44"
_TCNT
SECTION: ".abs_section_50"
_TC0
SECTION: ".abs_section_52"
_TC1
SECTION: ".abs_section_54"
_TC2
SECTION: ".abs_section_56"
_TC3
SECTION: ".abs_section_58"
_TC4
SECTION: ".abs_section_5a"
_TC5
SECTION: ".abs_section_5c"
_TC6
SECTION: ".abs_section_5e"
_TC7
SECTION: ".abs_section_62"
_PACNT
SECTION: ".abs_section_82"
_ATDCTL23
SECTION: ".abs_section_84"
_ATDCTL45
SECTION: ".abs_section_90"
_ATDDR0
SECTION: ".abs_section_92"
_ATDDR1
SECTION: ".abs_section_94"
_ATDDR2
SECTION: ".abs_section_96"
_ATDDR3
SECTION: ".abs_section_98"
_ATDDR4
SECTION: ".abs_section_9a"
_ATDDR5
SECTION: ".abs_section_9c"
_ATDDR6
SECTION: ".abs_section_9e"
_ATDDR7
SECTION: ".abs_section_c8"
_SCIBD
SECTION: ".abs_section_ec"
_PWMCNT01
SECTION: ".abs_section_ee"
_PWMCNT23
SECTION: ".abs_section_f0"
_PWMCNT45
SECTION: ".abs_section_f2"
_PWMPER01
SECTION: ".abs_section_f4"
_PWMPER23
SECTION: ".abs_section_f6"
_PWMPER45
SECTION: ".abs_section_f8"
_PWMDTY01
SECTION: ".abs_section_fa"
_PWMDTY23
SECTION: ".abs_section_fc"
_PWMDTY45
SECTION: ".abs_section_16e"
_CANRXTSR
SECTION: ".abs_section_17e"
_CANTXTSR
*********************************************************************************************
OBJECT LIST SORTED BY ADDRESS
Name Addr hSize dSize Ref Section RLIB
---------------------------------------------------------------------------------------------
_PORTAB 0 2 2 4 .abs_section_0
_DDRAB 2 2 2 2 .abs_section_2
_PORTE 8 1 1 0 .abs_section_8
_DDRE 9 1 1 0 .abs_section_9
_PEAR A 1 1 0 .abs_section_a
_MODE B 1 1 0 .abs_section_b
_PUCR C 1 1 0 .abs_section_c
_RDRIV D 1 1 0 .abs_section_d
_EBICTL E 1 1 0 .abs_section_e
_INITRM 10 1 1 0 .abs_section_10
_INITRG 11 1 1 0 .abs_section_11
_MISC 13 1 1 0 .abs_section_13
_ITCR 15 1 1 0 .abs_section_15
_ITEST 16 1 1 0 .abs_section_16
_VREGCTRL 19 1 1 0 .abs_section_19
_PARTID 1A 2 2 0 .abs_section_1a
_MEMSIZ0 1C 1 1 0 .abs_section_1c
_MEMSIZ1 1D 1 1 0 .abs_section_1d
_INTCR 1E 1 1 0 .abs_section_1e
_HPRIO 1F 1 1 0 .abs_section_1f
_DBGC1 20 1 1 0 .abs_section_20
_DBGSC 21 1 1 0 .abs_section_21
_DBGTB 22 2 2 0 .abs_section_22
_DBGCNT 24 1 1 0 .abs_section_24
_DBGCCX 25 1 1 0 .abs_section_25
_DBGCC 26 2 2 0 .abs_section_26
_DBGC2 28 1 1 0 .abs_section_28
_DBGC3 29 1 1 0 .abs_section_29
_DBGCAX 2A 1 1 0 .abs_section_2a
_DBGCA 2B 2 2 0 .abs_section_2b
_DBGCBX 2D 1 1 0 .abs_section_2d
_DBGCB 2E 2 2 0 .abs_section_2e
_PPAGE 30 1 1 0 .abs_section_30
_SYNR 34 1 1 0 .abs_section_34
_REFDV 35 1 1 0 .abs_section_35
_CRGFLG 37 1 1 0 .abs_section_37
_CRGINT 38 1 1 0 .abs_section_38
_CLKSEL 39 1 1 0 .abs_section_39
_PLLCTL 3A 1 1 0 .abs_section_3a
_RTICTL 3B 1 1 0 .abs_section_3b
_COPCTL 3C 1 1 0 .abs_section_3c
_ARMCOP 3F 1 1 0 .abs_section_3f
_TIOS 40 1 1 0 .abs_section_40
_CFORC 41 1 1 0 .abs_section_41
_OC7M 42 1 1 0 .abs_section_42
_OC7D 43 1 1 0 .abs_section_43
_TCNT 44 2 2 0 .abs_section_44
_TSCR1 46 1 1 0 .abs_section_46
_TTOV 47 1 1 0 .abs_section_47
_TCTL1 48 1 1 0 .abs_section_48
_TCTL2 49 1 1 0 .abs_section_49
_TCTL3 4A 1 1 0 .abs_section_4a
_TCTL4 4B 1 1 0 .abs_section_4b
_TIE 4C 1 1 0 .abs_section_4c
_TSCR2 4D 1 1 0 .abs_section_4d
_TFLG1 4E 1 1 0 .abs_section_4e
_TFLG2 4F 1 1 0 .abs_section_4f
_TC0 50 2 2 0 .abs_section_50
_TC1 52 2 2 0 .abs_section_52
_TC2 54 2 2 0 .abs_section_54
_TC3 56 2 2 0 .abs_section_56
_TC4 58 2 2 0 .abs_section_58
_TC5 5A 2 2 0 .abs_section_5a
_TC6 5C 2 2 0 .abs_section_5c
_TC7 5E 2 2 0 .abs_section_5e
_PACTL 60 1 1 0 .abs_section_60
_PAFLG 61 1 1 0 .abs_section_61
_PACNT 62 2 2 0 .abs_section_62
_ATDCTL23 82 2 2 0 .abs_section_82
_ATDCTL45 84 2 2 0 .abs_section_84
_ATDSTAT0 86 1 1 0 .abs_section_86
_ATDTEST1 89 1 1 0 .abs_section_89
_ATDSTAT1 8B 1 1 0 .abs_section_8b
_ATDDIEN 8D 1 1 0 .abs_section_8d
_PORTAD0 8F 1 1 0 .abs_section_8f
_ATDDR0 90 2 2 0 .abs_section_90
_ATDDR1 92 2 2 0 .abs_section_92
_ATDDR2 94 2 2 0 .abs_section_94
_ATDDR3 96 2 2 0 .abs_section_96
_ATDDR4 98 2 2 0 .abs_section_98
_ATDDR5 9A 2 2 0 .abs_section_9a
_ATDDR6 9C 2 2 0 .abs_section_9c
_ATDDR7 9E 2 2 0 .abs_section_9e
_SCIBD C8 2 2 0 .abs_section_c8
_SCICR1 CA 1 1 0 .abs_section_ca
_SCICR2 CB 1 1 0 .abs_section_cb
_SCISR1 CC 1 1 0 .abs_section_cc
_SCISR2 CD 1 1 0 .abs_section_cd
_SCIDRH CE 1 1 0 .abs_section_ce
_SCIDRL CF 1 1 0 .abs_section_cf
_SPICR1 D8 1 1 0 .abs_section_d8
_SPICR2 D9 1 1 0 .abs_section_d9
_SPIBR DA 1 1 0 .abs_section_da
_SPISR DB 1 1 0 .abs_section_db
_SPIDR DD 1 1 0 .abs_section_dd
_PWME E0 1 1 0 .abs_section_e0
_PWMPOL E1 1 1 0 .abs_section_e1
_PWMCLK E2 1 1 0 .abs_section_e2
_PWMPRCLK E3 1 1 0 .abs_section_e3
_PWMCAE E4 1 1 0 .abs_section_e4
_PWMCTL E5 1 1 0 .abs_section_e5
_PWMSCLA E8 1 1 0 .abs_section_e8
_PWMSCLB E9 1 1 0 .abs_section_e9
_PWMCNT01 EC 2 2 0 .abs_section_ec
_PWMCNT23 EE 2 2 0 .abs_section_ee
_PWMCNT45 F0 2 2 0 .abs_section_f0
_PWMPER01 F2 2 2 0 .abs_section_f2
_PWMPER23 F4 2 2 0 .abs_section_f4
_PWMPER45 F6 2 2 0 .abs_section_f6
_PWMDTY01 F8 2 2 0 .abs_section_f8
_PWMDTY23 FA 2 2 0 .abs_section_fa
_PWMDTY45 FC 2 2 0 .abs_section_fc
_PWMSDN FE 1 1 0 .abs_section_fe
_FCLKDIV 100 1 1 0 .abs_section_100
_FSEC 101 1 1 0 .abs_section_101
_FCNFG 103 1 1 0 .abs_section_103
_FPROT 104 1 1 0 .abs_section_104
_FSTAT 105 1 1 0 .abs_section_105
_FCMD 106 1 1 0 .abs_section_106
_CANCTL0 140 1 1 0 .abs_section_140
_CANCTL1 141 1 1 0 .abs_section_141
_CANBTR0 142 1 1 0 .abs_section_142
_CANBTR1 143 1 1 0 .abs_section_143
_CANRFLG 144 1 1 0 .abs_section_144
_CANRIER 145 1 1 0 .abs_section_145
_CANTFLG 146 1 1 0 .abs_section_146
_CANTIER 147 1 1 0 .abs_section_147
_CANTARQ 148 1 1 0 .abs_section_148
_CANTAAK 149 1 1 0 .abs_section_149
_CANTBSEL 14A 1 1 0 .abs_section_14a
_CANIDAC 14B 1 1 0 .abs_section_14b
_CANRXERR 14E 1 1 0 .abs_section_14e
_CANTXERR 14F 1 1 0 .abs_section_14f
_CANIDAR0 150 1 1 0 .abs_section_150
_CANIDAR1 151 1 1 0 .abs_section_151
_CANIDAR2 152 1 1 0 .abs_section_152
_CANIDAR3 153 1 1 0 .abs_section_153
_CANIDMR0 154 1 1 0 .abs_section_154
_CANIDMR1 155 1 1 0 .abs_section_155
_CANIDMR2 156 1 1 0 .abs_section_156
_CANIDMR3 157 1 1 0 .abs_section_157
_CANIDAR4 158 1 1 0 .abs_section_158
_CANIDAR5 159 1 1 0 .abs_section_159
_CANIDAR6 15A 1 1 0 .abs_section_15a
_CANIDAR7 15B 1 1 0 .abs_section_15b
_CANIDMR4 15C 1 1 0 .abs_section_15c
_CANIDMR5 15D 1 1 0 .abs_section_15d
_CANIDMR6 15E 1 1 0 .abs_section_15e
_CANIDMR7 15F 1 1 0 .abs_section_15f
_CANRXIDR0 160 1 1 0 .abs_section_160
_CANRXIDR1 161 1 1 0 .abs_section_161
_CANRXIDR2 162 1 1 0 .abs_section_162
_CANRXIDR3 163 1 1 0 .abs_section_163
_CANRXDSR0 164 1 1 0 .abs_section_164
_CANRXDSR1 165 1 1 0 .abs_section_165
_CANRXDSR2 166 1 1 0 .abs_section_166
_CANRXDSR3 167 1 1 0 .abs_section_167
_CANRXDSR4 168 1 1 0 .abs_section_168
_CANRXDSR5 169 1 1 0 .abs_section_169
_CANRXDSR6 16A 1 1 0 .abs_section_16a
_CANRXDSR7 16B 1 1 0 .abs_section_16b
_CANRXDLR 16C 1 1 0 .abs_section_16c
_CANRXTSR 16E 2 2 0 .abs_section_16e
_CANTXIDR0 170 1 1 0 .abs_section_170
_CANTXIDR1 171 1 1 0 .abs_section_171
_CANTXIDR2 172 1 1 0 .abs_section_172
_CANTXIDR3 173 1 1 0 .abs_section_173
_CANTXDSR0 174 1 1 0 .abs_section_174
_CANTXDSR1 175 1 1 0 .abs_section_175
_CANTXDSR2 176 1 1 0 .abs_section_176
_CANTXDSR3 177 1 1 0 .abs_section_177
_CANTXDSR4 178 1 1 0 .abs_section_178
_CANTXDSR5 179 1 1 0 .abs_section_179
_CANTXDSR6 17A 1 1 0 .abs_section_17a
_CANTXDSR7 17B 1 1 0 .abs_section_17b
_CANTXDLR 17C 1 1 0 .abs_section_17c
_CANTXTBPR 17D 1 1 0 .abs_section_17d
_CANTXTSR 17E 2 2 0 .abs_section_17e
_PTT 240 1 1 0 .abs_section_240
_PTIT 241 1 1 0 .abs_section_241
_DDRT 242 1 1 0 .abs_section_242
_RDRT 243 1 1 0 .abs_section_243
_PERT 244 1 1 0 .abs_section_244
_PPST 245 1 1 0 .abs_section_245
_MODRR 247 1 1 0 .abs_section_247
_PTS 248 1 1 0 .abs_section_248
_PTIS 249 1 1 0 .abs_section_249
_DDRS 24A 1 1 0 .abs_section_24a
_RDRS 24B 1 1 0 .abs_section_24b
_PERS 24C 1 1 0 .abs_section_24c
_PPSS 24D 1 1 0 .abs_section_24d
_WOMS 24E 1 1 0 .abs_section_24e
_PTM 250 1 1 0 .abs_section_250
_PTIM 251 1 1 0 .abs_section_251
_DDRM 252 1 1 0 .abs_section_252
_RDRM 253 1 1 0 .abs_section_253
_PERM 254 1 1 0 .abs_section_254
_PPSM 255 1 1 0 .abs_section_255
_WOMM 256 1 1 0 .abs_section_256
_PTP 258 1 1 0 .abs_section_258
_PTIP 259 1 1 0 .abs_section_259
_DDRP 25A 1 1 0 .abs_section_25a
_RDRP 25B 1 1 0 .abs_section_25b
_PERP 25C 1 1 0 .abs_section_25c
_PPSP 25D 1 1 0 .abs_section_25d
_PIEP 25E 1 1 0 .abs_section_25e
_PIFP 25F 1 1 0 .abs_section_25f
_PTJ 268 1 1 0 .abs_section_268
_PTIJ 269 1 1 0 .abs_section_269
_DDRJ 26A 1 1 0 .abs_section_26a
_RDRJ 26B 1 1 0 .abs_section_26b
_PERJ 26C 1 1 0 .abs_section_26c
_PPSJ 26D 1 1 0 .abs_section_26d
_PIEJ 26E 1 1 0 .abs_section_26e
_PIFJ 26F 1 1 0 .abs_section_26f
_PTAD 270 1 1 0 .abs_section_270
_PTIAD 271 1 1 0 .abs_section_271
_DDRAD 272 1 1 0 .abs_section_272
_RDRAD 273 1 1 0 .abs_section_273
_PERAD 274 1 1 0 .abs_section_274
_PPSAD 275 1 1 0 .abs_section_275
Init C000 29 41 1 .init
_Startup C029 8 8 0 .init
main C03B 3A 58 1 .text
*********************************************************************************************
UNUSED-OBJECTS SECTION
---------------------------------------------------------------------------------------------
*********************************************************************************************
COPYDOWN SECTION
---------------------------------------------------------------------------------------------
------- ROM-ADDRESS: 0xC075 ---- SIZE 2 ---
Filling bytes inserted
0000
*********************************************************************************************
OBJECT-DEPENDENCIES SECTION
---------------------------------------------------------------------------------------------
Init USES _startupData
_Startup USES __SEG_END_SSTACK Init main
main USES _DDRAB _PORTAB
*********************************************************************************************
DEPENDENCY TREE
*********************************************************************************************
main and _Startup Group
|
+- main
|
+- _Startup
|
+- Init
|
+- main (see above)

*********************************************************************************************
STATISTIC SECTION
---------------------------------------------------------------------------------------------
ExeFile:
--------
Number of blocks to be downloaded: 5
Total size of all blocks to be downloaded: 121
dip_switch_c/C_Layout.hwl
OPEN source 0 0 60 39
Source < attributes MARKS off
OPEN assembly 60 0 40 31
Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C
OPEN procedure 0 39 60 17
Procedure < attributes VALUES on,TYPES off
OPEN register 60 31 40 25
Register < attributes FORMAT AUTO,COMPLEMENT None
OPEN memory 60 56 40 22
Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80
OPEN data 0 56 60 22
Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16
OPEN data 0 78 60 22
Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16
OPEN command 60 78 40 22
Command < attributes CACHESIZE 1000
bckcolor 50331647
font 'Courier New' 9 BLACK
AUTOSIZE on
ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory
dip_switch_c/cmd/Full_Chip_Simulation_Postload.cmd
// After load the commands written below will be executed
dip_switch_c/cmd/Full_Chip_Simulation_Preload.cmd
// Before load the commands written below will be executed
dip_switch_c/cmd/Full_Chip_Simulation_Reset.cmd
// After reset the commands written below will be executed
dip_switch_c/cmd/Full_Chip_Simulation_SetCPU.cmd
// At startup the commands written below will be executed
dip_switch_c/cmd/Full_Chip_Simulation_Startup.cmd
// At startup the commands written below will be executed
dip_switch_c/Default.mem
dip_switch_c/dip_switch_c.mcp
dip_switch_c/dip_switch_c_Data/CWSettingsWindows.stg
dip_switch_c/dip_switch_c_Data/Standard/ObjectCode/datapage.c.o
dip_switch_c/dip_switch_c_Data/Standard/ObjectCode/main.c.o
dip_switch_c/dip_switch_c_Data/Standard/ObjectCode/mc9s12c32.c.o
dip_switch_c/dip_switch_c_Data/Standard/ObjectCode/Start12.c.o
dip_switch_c/dip_switch_c_Data/Standard/TargetDataWindows.tdt
dip_switch_c/Full_Chip_Simulation.ini
[Environment Variables]
GENPATH={Project}Sources;{Compiler}lib\hc12c\src;{Compiler}lib\hc12c\include;{Compiler}lib\hc12c\lib;{Compiler}lib\xgatec\src;{Compiler}lib\xgatec\include;{Compiler}lib\xgatec\lib
LIBPATH={Compiler}lib\hc12c\include;{Compiler}lib\xgatec\include
OBJPATH={Project}bin
TEXTPATH={Project}bin
ABSPATH={Project}bin
[HI-WAVE]
Target=sim
Layout=C_layout.hwl
LoadDialogOptions=AUTOERASEANDFLASH RUNANDSTOPAFTERLOAD="main"
CPU=HC12
MainFrame=0,1,-1,-1,-1,-1,100,100,1078,656
TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806
[Simulator]
CMDFILE0=CMDFILE STARTUP ON ".\cmd\Full_Chip_Simulation_startup.cmd"
[Simulator HC12]
CMDFILE0=CMDFILE RESET ON ".\cmd\Full_Chip_Simulation_reset.cmd"
CMDFILE1=CMDFILE PRELOAD ON ".\cmd\Full_Chip_Simulation_preload.cmd"
CMDFILE2=CMDFILE POSTLOAD ON ".\cmd\Full_Chip_Simulation_postload.cmd"
CMDFILE3=CMDFILE SETCPU ON ".\cmd\Full_Chip_Simulation_setcpu.cmd"
HCS12_SUPPORT=1
FCS=MC9S12C32
dip_switch_c/prm/burner.bbl
/* logical s-record file */
OPENFILE "%ABS_FILE%.s19"
format=motorola
busWidth=1
origin=0
len=0x1000000
destination=0
SRECORD=Sx
SENDBYTE 1 "%ABS_FILE%"
CLOSE
/* physical s-record file */
OPENFILE "%ABS_FILE%.phy"
format = motorola
busWidth = 1
len = 0x4000
/* logical non banked flash at $4000 and $C000 to physical */
origin = 0x004000
destination = 0x0F8000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x00C000
destination = 0x0FC000
SENDBYTE 1 "%ABS_FILE%"
/* physical FTS512K flash window to physical
origin = 0x008000
destination = 0x080000
SENDBYTE 1 "%ABS_FILE%"
*/
/* physical FTS256K parts flash window to physical
origin = 0x008000
destination = 0x0C0000
SENDBYTE 1 "%ABS_FILE%"
*/
/* physical FTS128K parts flash window to physical
origin = 0x008000
destination = 0x0E0000
SENDBYTE 1 "%ABS_FILE%"
*/
/* physical FTS64K parts flash window to physical
origin = 0x008000
destination = 0x0F0000
SENDBYTE 1 "%ABS_FILE%"
*/
/* physical FTS32K parts flash window to physical
origin = 0x008000
destination = 0x0F8000
SENDBYTE 1 "%ABS_FILE%"
*/
/* logical 512 kB banked flash to physical */
origin = 0x208000
destination = 0x080000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x218000
destination = 0x084000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x228000
destination = 0x088000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x238000
destination = 0x08C000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x248000
destination = 0x090000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x258000
destination = 0x094000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x268000
destination = 0x098000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x278000
destination = 0x09C000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x288000
destination = 0x0A0000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x298000
destination = 0x0A4000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x2A8000
destination = 0x0A8000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x2B8000
destination = 0x0AC000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x2C8000
destination = 0x0B0000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x2D8000
destination = 0x0B4000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x2E8000
destination = 0x0B8000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x2F8000
destination = 0x0BC000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x308000
destination = 0x0C0000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x318000
destination = 0x0C4000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x328000
destination = 0x0C8000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x338000
destination = 0x0CC000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x348000
destination = 0x0D0000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x358000
destination = 0x0D4000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x368000
destination = 0x0D8000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x378000
destination = 0x0DC000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x388000
destination = 0x0E0000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x398000
destination = 0x0E4000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x3A8000
destination = 0x0E8000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x3B8000
destination = 0x0EC000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x3C8000
destination = 0x0F0000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x3D8000
destination = 0x0F4000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x3E8000
destination = 0x0F8000
SENDBYTE 1 "%ABS_FILE%"
origin = 0x3F8000
destination = 0x0FC000
SENDBYTE 1 "%ABS_FILE%"
CLOSE
dip_switch_c/prm/Project.prm
/* This is a linker parameter file for the MC9S12C32 */
NAMES END /* CodeWarrior will pass all the needed files to the linker by command line. But here you may add your own files too. */
SEGMENTS /* Here all RAM/ROM areas of the device are listed. Used in PLACEMENT below. */
/* Register space */
/* IO_SEG = PAGED 0x0000 TO 0x03FF; intentionally not defined */
/* RAM */
RAM = READ_WRITE 0x0800 TO 0x0FFF;
/* non-paged FLASHs */
ROM_4000 = READ_ONLY 0x4000 TO 0x7FFF;
ROM_C000 = READ_ONLY 0xC000 TO 0xFEFF;
/* VECTORS = READ_ONLY 0xFF00 TO 0xFFFF; intentionally not defined: used for VECTOR commands below */
//OSVECTORS = READ_ONLY 0xFF8A TO 0xFFFF; /* OSEK interrupt vectors (use your vector.o) */
END
PLACEMENT /* here all predefined and user segments are placed into the SEGMENTS defined above. */
_PRESTART, /* Used in HIWARE format: jump to _Startup at the code start */
STARTUP, /* startup data structures */
ROM_VAR, /* constant variables */
STRINGS, /* string literals */
VIRTUAL_TABLE_SEGMENT, /* C++ virtual table segment */
//.ostext, /* OSEK */
DEFAULT_ROM, NON_BANKED, /* runtime routines which must not be banked */
OTHER_ROM ,
COPY /* copy down information: how to initialize variables */
/* in case you want to use ROM_4000 here as well, make sure
that all files (incl. library files) are compiled with the
option: -OnB=b */
INTO ROM_C000/*, ROM_4000*/;
//.stackstart, /* eventually used for OSEK kernel awareness: Main-Stack Start */
SSTACK, /* allocate stack first to avoid overwriting variables on overflow */
//.stackend, /* eventually used for OSEK kernel awareness: Main-Stack End */
DEFAULT_RAM INTO RAM;
//.vectors INTO OSVECTORS; /* OSEK */
END
ENTRIES /* keep the following unreferenced variables */
/* OSEK: always allocate the vector table and all dependent objects */
//_vectab OsBuildNumber _OsOrtiStackStart _OsOrtiStart
END
STACKSIZE 0x100
VECTOR 0 _Startup /* reset vector: this is the default entry point for a C/C++ application. */
//VECTOR 0 Entry /* reset vector: this is the default entry point for an Assembly application. */
//INIT Entry /* for assembly applications: that this is as well the initialization entry point */
dip_switch_c/Sources/datapage.c
/******************************************************************************
FILE : datapage.c
PURPOSE : paged data access runtime routines
MACHINE : Freescale 68HC12 (Target)
LANGUAGE : ANSI-C
HISTORY : 21.7.96 first version created
******************************************************************************/
#include "hidef.h"
#include "non_bank.sgm"
#include "runtime.sgm"
/*lint --e{957} , MISRA 8.1 REQ, these are runtime support functions and, as such, are not meant to be called in user code; they are only invoked via jumps, in compiler-generated code */
/*lint -estring(553, __OPTION_ACTIVE__) , MISRA 19.11 REQ , __OPTION_ACTIVE__ is a built-in compiler construct to check for active compiler options */
#ifndef __HCS12X__ /* it's different for the HCS12X. See the text below at the #else // __HCS12X__ */
/*
According to the -Cp option of the compiler the
__DPAGE__, __PPAGE__ and __EPAGE__ macros are defined.
If none of them is given as argument, then no page accesses should occur and
this runtime routine should not be used !
To be on the save side, the runtime routines are created anyway.
*/
/* Compile with option -DHCS12 to activate this code */
#if defined(HCS12) || defined(_HCS12) || defined(__HCS12__)
#ifndef PPAGE_ADDR
#ifdef __PPAGE_ADR__
#define PPAGE_ADDR __PPAGE_ADR__
#else
#define PPAGE_ADDR (0x30 + REGISTER_BASE)
#endif
#endif
#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */
#define __PPAGE__
#endif
/* Compile with option -DDG128 to activate this code */
#elif defined DG128 /* HC912DG128 derivative has PPAGE register only at 0xFF */
#ifndef PPAGE_ADDR
#define PPAGE_ADDR (0xFF+REGISTER_BASE)
#endif
#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */
#define __PPAGE__
#endif
#elif defined(HC812A4)
/* all setting default to A4 already */
#endif
#if !defined(__EPAGE__) && !defined(__PPAGE__) && !defined(__DPAGE__)
/* as default use all page registers */
#define __DPAGE__
#define __EPAGE__
#define __PPAGE__
#endif
/* modify the following defines to your memory configuration */
#define EPAGE_LOW_BOUND 0x400u
#define EPAGE_HIGH_BOUND 0x7ffu
#define DPAGE_LOW_BOUND 0x7000u
#define DPAGE_HIGH_BOUND 0x7fffu
#define PPAGE_LOW_BOUND (DPAGE_HIGH_BOUND+1u)
#define PPAGE_HIGH_BOUND 0xBFFFu
#ifndef REGISTER_BASE
#define REGISTER_BASE 0x0u
#endif
#ifndef DPAGE_ADDR
#define DPAGE_ADDR (0x34u+REGISTER_BASE)
#endif
#ifndef EPAGE_ADDR
#define EPAGE_ADDR (0x36u+REGISTER_BASE)
#endif
#ifndef PPAGE_ADDR
#define PPAGE_ADDR (0x35u+REGISTER_BASE)
#endif
/*
The following parts about the defines are assumed in the code of _GET_PAGE_REG :
- the memory region controlled by DPAGE is above the area controlled by the EPAGE and
below the area controlled by the PPAGE.
- the lower bound of the PPAGE area is equal to be the higher bound of the DPAGE area + 1
*/
#if (EPAGE_LOW_BOUND >= EPAGE_HIGH_BOUND) || (EPAGE_HIGH_BOUND >= DPAGE_LOW_BOUND) || (DPAGE_LOW_BOUND >= DPAGE_HIGH_BOUND) || (DPAGE_HIGH_BOUND >= PPAGE_LOW_BOUND) || (PPAGE_LOW_BOUND >= PPAGE_HIGH_BOUND)
#error /* please adapt _GET_PAGE_REG for this non default page configuration */
#endif
#if (DPAGE_HIGH_BOUND+1u) != PPAGE_LOW_BOUND
#error /* please adapt _GET_PAGE_REG for this non default page configuration */
#endif
/* this module does either control if any access is in the bounds of the specified page or */
/* ,if only one page is specified, just use this page. */
/* This behavior is controlled by the define USE_SEVERAL_PAGES. */
/* If !USE_SEVERAL_PAGES does increase the performance significantly */
/* NOTE : When !USE_SEVERAL_PAGES, the page is also set for accesses outside of the area controlled */
/* by this single page. But this is should not cause problems because the page is restored to the old value before any other access could occur */
#if !defined(__DPAGE__) && !defined(__EPAGE__) && !defined(__PPAGE__)
/* no page at all is specified */
/* only specifying the right pages will speed up these functions a lot */
#define USE_SEVERAL_PAGES 1
#elif (defined(__DPAGE__) && defined(__EPAGE__)) || (defined(__DPAGE__) && defined(__PPAGE__)) || (defined(__EPAGE__) && defined(__PPAGE__))
/* more than one page register is used */
#define USE_SEVERAL_PAGES 1
#else
#define USE_SEVERAL_PAGES 0
#if defined(__DPAGE__) /* check which pages are used */
#define PAGE_ADDR PPAGE_ADDR
#elif defined(__EPAGE__)
#define PAGE_ADDR EPAGE_ADDR
#elif defined(__PPAGE__)
#define PAGE_ADDR PPAGE_ADDR
#else /* we do not know which page, decide it at runtime */
#error /* must not happen */
#endif
#endif
#if USE_SEVERAL_PAGES /* only needed for several pages support */
/*--------------------------- _GET_PAGE_REG --------------------------------
Runtime routine to detect the right register depending on the 16 bit offset part
of an address.
This function is only used by the functions below.
Depending on the compiler options -Cp different versions of _GET_PAGE_REG are produced.
Arguments :
- Y : offset part of an address
Result :
if address Y is controlled by a page register :
- X : address of page register if Y is controlled by an page register
- Zero flag cleared
- all other registers remain unchanged
if address Y is not controlled by a page register :
- Zero flag is set
- all registers remain unchanged
--------------------------- _GET_PAGE_REG ----------------------------------*/
#if defined(__DPAGE__)
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */
asm {
L_DPAGE:
CPY #DPAGE_LOW_BOUND ;/* test of lower bound of DPAGE */
#if defined(__EPAGE__)
BLO L_EPAGE ;/* EPAGE accesses are possible */
#else
BLO L_NOPAGE ;/* no paged memory below accesses */
#endif
CPY #DPAGE_HIGH_BOUND ;/* test of higher bound DPAGE/lower bound PPAGE */
#if defined(__PPAGE__)
BHI L_PPAGE ;/* EPAGE accesses are possible */
#else
BHI L_NOPAGE ;/* no paged memory above accesses */
#endif
FOUND_DPAGE:
LDX #DPAGE_ADDR ;/* load page register address and clear zero flag */
RTS
#if defined(__PPAGE__)
L_PPAGE:
CPY #PPAGE_HIGH_BOUND ;/* test of higher bound of PPAGE */
BHI L_NOPAGE
FOUND_PPAGE:
LDX #PPAGE_ADDR ;/* load page register address and clear zero flag */
RTS
#endif
#if defined(__EPAGE__)
L_EPAGE:
CPY #EPAGE_LOW_BOUND ;/* test of lower bound of EPAGE */
BLO L_NOPAGE
CPY #EPAGE_HIGH_BOUND ;/* test of higher bound of EPAGE */
BHI L_NOPAGE
FOUND_EPAGE:
LDX #EPAGE_ADDR ;/* load page register address and clear zero flag */
RTS
#endif
L_NOPAGE:
ORCC #0x04 ;/* sets zero flag */
RTS
}
}
#else /* !defined(__DPAGE__) */
#if defined( __PPAGE__ )
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
static void NEAR _GET_PAGE_REG(void) {    /*lint -esym(528, _GET_PAGE_REG) used in asm code */
asm {
L_PPAGE:
CPY #PPAGE_LOW_BOUND ;/* test of lower bound of PPAGE */
#if defined( __EPAGE__ )
BLO L_EPAGE
#else
BLO L_NOPAGE ;/* no paged memory below */
#endif
CPY #PPAGE_HIGH_BOUND ;/* test of higher bound PPAGE */
BHI L_NOPAGE
FOUND_PPAGE:
LDX #PPAGE_ADDR ;/* load page register address and clear zero flag */
RTS
#if defined( __EPAGE__ )
L_EPAGE:
CPY #EPAGE_LOW_BOUND ;/* test of lower bound of EPAGE */
BLO L_NOPAGE
CPY #EPAGE_HIGH_BOUND ;/* test of higher bound of EPAGE */
BHI L_NOPAGE
FOUND_EPAGE:
LDX #EPAGE_ADDR ;/* load page register address and clear zero flag */
RTS
#endif
L_NOPAGE: ;/* not in any allowed page area */
;/* its a far access to a non paged variable */
ORCC #0x04 ;/* sets zero flag */
RTS
}
}
#else /* !defined(__DPAGE__ ) && !defined( __PPAGE__) */
#if defined(__EPAGE__)
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */
asm {
L_EPAGE:
CPY #EPAGE_LOW_BOUND ;/* test of lower bound of EPAGE */
BLO L_NOPAGE
CPY #EPAGE_HIGH_BOUND ;/* test of higher bound of EPAGE */
BHI L_NOPAGE
FOUND_EPAGE:
LDX #EPAGE_ADDR ;/* load page register address and clear zero flag */
RTS
L_NOPAGE: ;/* not in any allowed page area */
;/* its a far access to a non paged variable */
ORCC #0x04 ;/* sets zero flag */
RTS
}
}
#endif /* defined(__EPAGE__) */
#endif /* defined(__PPAGE__) */
#endif /* defined(__DPAGE__) */
#endif /* USE_SEVERAL_PAGES */
/*--------------------------- _SET_PAGE --------------------------------
Runtime routine to set the right page register. This routine is used if the compiler
does not know the right page register, i.e. if the option -Cp is used for more than
one page register or if the runtime option is used for one of the -Cp options.
Arguments :
- offset part of an address in the Y register
- page part of an address in the B register
Result :
- page part written into the correct page register.
- the old page register content is destroyed
- all processor registers remains unchanged
--------------------------- _SET_PAGE ----------------------------------*/
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _SET_PAGE(void) {
#if USE_SEVERAL_PAGES
asm {
PSHX ;/* save X register */
__PIC_JSR(_GET_PAGE_REG)
BEQ L_NOPAGE
STAB 0,X ;/* set page register */
L_NOPAGE:
PULX ;/* restore X register */
RTS
}
#else /* USE_SEVERAL_PAGES */
asm {
STAB PAGE_ADDR ;/* set page register */
RTS
}
#endif /* USE_SEVERAL_PAGES */
}
/*--------------------------- _LOAD_FAR_8 --------------------------------
This runtime routine is used to access paged memory via a runtime function.
It may also be used if the compiler option -Cp is not used with the runtime argument.
Arguments :
- offset part of an address in the Y register
- page part of an address in the B register
Result :
- value to be read in the B register
- all other registers remains unchanged
- all page register still contain the same value
--------------------------- _LOAD_FAR_8 ----------------------------------*/
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _LOAD_FAR_8(void) {
#if USE_SEVERAL_PAGES
asm {
PSHX ;/* save X register */
__PIC_JSR(_GET_PAGE_REG)
BEQ L_NOPAGE
PSHA ;/* save A register */
LDAA 0,X ;/* save page register */
STAB 0,X ;/* set page register */
LDAB 0,Y ;/* actual load, overwrites page */
STAA 0,X ;/* restore page register */
PULA ;/* restore A register */
PULX ;/* restore X register */
RTS
L_NOPAGE:
LDAB 0,Y ;/* actual load, overwrites page */
PULX ;/* restore X register */
RTS
}
#else /* USE_SEVERAL_PAGES */
asm {
PSHA ;/* save A register */
LDAA PAGE_ADDR ;/* save page register */
STAB PAGE_ADDR ;/* set page register */
LDAB 0,Y ;/* actual load, overwrites page */
STAA PAGE_ADDR ;/* restore page register */
PULA ;/* restore A register */
RTS
}
#endif /* USE_SEVERAL_PAGES */
}
/*--------------------------- _LOAD_FAR_16 --------------------------------
This runtime routine is used to access paged memory via a runtime function.
It may also be used if the compiler option -Cp is not used with the runtime argument.
Arguments :
- offset part of an address in the Y register
- page part of an address in the B register
Result :
- value to be read in the Y register
- all other registers remains unchanged
- all page register still contain the same value
--------------------------- _LOAD_FAR_16 ----------------------------------*/
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _LOAD_FAR_16(void) {
#if USE_SEVERAL_PAGES
asm {
PSHX ;/* save X register */
__PIC_JSR(_GET_PAGE_REG)
BEQ L_NOPAGE
PSHA ;/* save A register */
LDAA 0,X ;/* save page register */
STAB 0,X ;/* set page register */
LDY 0,Y ;/* actual load, overwrites address */
STAA 0,X ;/* restore page register */
PULA ;/* restore A register */
PULX ;/* restore X register */
RTS
L_NOPAGE:
LDY 0,Y ;/* actual load, overwrites address */
PULX ;/* restore X register */
RTS
}
#else /* USE_SEVERAL_PAGES */
asm {
PSHA ;/* save A register */
LDAA PAGE_ADDR ;/* save page register */
STAB PAGE_ADDR ;/* set page register */
LDY 0,Y ;/* actual load, overwrites address */
STAA PAGE_ADDR ;/* restore page register */
PULA ;/* restore A register */
RTS
}
#endif /* USE_SEVERAL_PAGES */
}
/*--------------------------- _LOAD_FAR_24 --------------------------------
This runtime routine is used to access paged memory via a runtime function.
It may also be used if the compiler option -Cp is not used with the runtime argument.
Arguments :
- offset part of an address in the Y register
- page part of an address in the B register
Result :
- value to be read in the Y:B registers
- all other registers remains unchanged
- all page register still contain the same value
--------------------------- _LOAD_FAR_24 ----------------------------------*/
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _LOAD_FAR_24(void) {
#if USE_SEVERAL_PAGES
asm {
PSHX ;/* save X register */
__PIC_JSR(_GET_PAGE_REG)
BEQ L_NOPAGE
PSHA ;/* save A register */
LDAA 0,X ;/* save page register */
STAB 0,X ;/* set page register */
LDAB 0,Y ;/* actual load, overwrites page of address */
LDY 1,Y ;/* actual load, overwrites offset of address */
STAA 0,X ;/* restore page register */
PULA ;/* restore A register */
PULX ;/* restore X register */
RTS
L_NOPAGE:
LDAB 0,Y ;/* actual load, overwrites page of address */
LDY 1,Y ;/* actual load, overwrites offset of address */
PULX ;/* restore X register */
RTS
}
#else /* USE_SEVERAL_PAGES */
asm {
PSHA ;/* save A register */
LDAA PAGE_ADDR ;/* save page register */
STAB PAGE_ADDR ;/* set page register */
LDAB 0,Y ;/* actual load, overwrites page of address */
LDY 1,Y ;/* actual load, overwrites offset of address */
STAA PAGE_ADDR ;/* restore page register */
PULA ;/* restore A register */
RTS
}
#endif /* USE_SEVERAL_PAGES */
}
/*--------------------------- _LOAD_FAR_32 --------------------------------
This runtime routine is used to access paged memory via a runtime function.
It may also be used if the compiler option -Cp is not used with the runtime argument.
Arguments :
- offset part of an address in the Y register
- page part of an address in the B register
Result :
- low 16 bit of value to be read in the D registers
- high 16 bit of value to be read in the Y registers
- all other registers remains unchanged
- all page register still contain the same value
--------------------------- _LOAD_FAR_32 ----------------------------------*/
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _LOAD_FAR_32(void) {
#if USE_SEVERAL_PAGES
asm {
PSHX ;/* save X register */
__PIC_JSR(_GET_PAGE_REG)
BEQ L_NOPAGE
LDAA 0,X ;/* save page register */
PSHA ;/* put it onto the stack */
STAB 0,X ;/* set page register */
LDD 2,Y ;/* actual load, low word */
LDY 0,Y ;/* actual load, high word */
MOVB 1,SP+,0,X ;/* restore page register */
PULX ;/* restore X register */
RTS
L_NOPAGE:
LDD 2,Y ;/* actual load, low word */
LDY 0,Y ;/* actual load, high word */
PULX ;/* restore X register */
RTS
}
#else /* USE_SEVERAL_PAGES */
asm {
LDAA PAGE_ADDR ;/* save page register */
PSHA ;/* put it onto the stack */
STAB PAGE_ADDR ;/* set page register */
LDD 2,Y ;/* actual load, low word */
LDY 0,Y ;/* actual load, high word */
MOVB 1,SP+,PAGE_ADDR ;/* restore page register */
RTS
}
#endif /* USE_SEVERAL_PAGES */
}
/*--------------------------- _STORE_FAR_8 --------------------------------
This runtime routine is used to access paged memory via a runtime function.
It may also be used if the compiler option -Cp is not used with the runtime argument.
Arguments :
- offset part of an address in the Y register
- page part of an address in the B register
- value to be stored in the B register
Result :
- value stored at the address
- all registers remains unchanged
- all page register still contain the same value
--------------------------- _STORE_FAR_8 ----------------------------------*/
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _STORE_FAR_8(void) {
#if USE_SEVERAL_PAGES
asm {
PSHX ;/* save X register */
__PIC_JSR(_GET_PAGE_REG)
BEQ L_NOPAGE
PSHB ;/* save B register */
LDAB 0,X ;/* save page register */
MOVB 0,SP, 0,X ;/* set page register */
STAA 0,Y ;/* store the value passed in A */
STAB 0,X ;/* restore page register */
PULB ;/* restore B register */
PULX ;/* restore X register */
RTS
L_NOPAGE:
STAA 0,Y ;/* store the value passed in A */
PULX ;/* restore X register */
RTS
}
#else /* USE_SEVERAL_PAGES */
asm {
PSHB ;/* save A register */
LDAB PAGE_ADDR ;/* save page register */
MOVB 0,SP,PAGE_ADDR ;/* set page register */
STAA 0,Y ;/* store the value passed in A */
STAB PAGE_ADDR ;/* restore page register */
PULB ;/* restore B register */
RTS
}
#endif /* USE_SEVERAL_PAGES */
}
/*--------------------------- _STORE_FAR_16 --------------------------------
This runtime routine is used to access paged memory via a runtime function.
It may also be used if the compiler option -Cp is not used with the runtime argument.
Arguments :
- offset part of an address in the Y register
- page part of an address in the B register
- value to be stored in the X register
Result :
- value stored at the address
- all registers remains unchanged
- all page register still contain the same value
--------------------------- _STORE_FAR_16 ----------------------------------*/
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _STORE_FAR_16(void) {
#if USE_SEVERAL_PAGES
asm {
PSHX ;/* save X register */
__PIC_JSR(_GET_PAGE_REG)
BEQ L_NOPAGE
PSHA
LDAA 0,X ;/* save page register */
STAB 0,X ;/* set page register */
MOVW 1,SP,0,Y ;/* store the value passed in X */
STAA 0,X ;/* restore page register */
PULA ;/* restore A register */
PULX ;/* restore X register */
RTS
L_NOPAGE:
STX 0,Y ;/* store the value passed in X */
PULX ;/* restore X register */
RTS
}
#else /* USE_SEVERAL_PAGES */
asm {
PSHA ;/* save A register */
LDAA PAGE_ADDR ;/* save page register */
STAB PAGE_ADDR ;/* set page register */
STX 0,Y ;/* store the value passed in X */
STAA PAGE_ADDR ;/* restore page register */
PULA ;/* restore A register */
RTS
}
#endif /* USE_SEVERAL_PAGES */
}
/*--------------------------- _STORE_FAR_24 --------------------------------
This runtime routine is used to access paged memory via a runtime function.
It may also be used if the compiler option -Cp is not used with the runtime argument.
Arguments :
- offset part of an address in the Y register
- page part of an address in the B register
- value to be stored in the X:A registers (X : low 16 bit, A : high 8 bit)
Result :
- value stored at the address
- all registers remains unchanged
- all page register still contain the same value
--------------------------- _STORE_FAR_24 ----------------------------------*/
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _STORE_FAR_24(void) {
#if USE_SEVERAL_PAGES
asm {
PSHX ;/* save X register */
__PIC_JSR(_GET_PAGE_REG)
BEQ L_NOPAGE
PSHA
LDAA 0,X ;/* save page register */
STAB 0,X ;/* set page register */
MOVW 1,SP, 1,Y ;/* store the value passed in X */
MOVB 0,SP, 0,Y ;/* store the value passed in A */
STAA 0,X ;/* restore page register */
PULA ;/* restore A register */
PULX ;/* restore X register */
RTS
L_NOPAGE:
STX 1,Y ;/* store the value passed in X */
STAA 0,Y ;/* store the value passed in X */
PULX ;/* restore X register */
RTS
}
#else /* USE_SEVERAL_PAGES */
asm {
PSHA ;/* save A register */
LDAA PAGE_ADDR ;/* save page register */
STAB PAGE_ADDR ;/* set page register */
MOVB 0,SP, 0,Y ;/* store the value passed in A */
STX 1,Y ;/* store the value passed in X */
STAA PAGE_ADDR ;/* restore page register */
PULA ;/* restore A register */
RTS
}
#endif /* USE_SEVERAL_PAGES */
}
/*--------------------------- _STORE_FAR_32 --------------------------------
This runtime routine is used to access paged memory via a runtime function.
It may also be used if the compiler option -Cp is not used with the runtime argument.
Arguments :
- offset part of an address in the Y register
- page part of an address is on the stack at 3,SP (just below the return address)
- value to be stored in the X:D registers (D : low 16 bit, X : high 16 bit)
Result :
- value stored at the address
- all registers remains unchanged
- the page part is removed from the stack
- all page register still contain the same value
--------------------------- _STORE_FAR_32 ----------------------------------*/
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _STORE_FAR_32(void) {
#if USE_SEVERAL_PAGES
asm {
PSHX ;/* save X register */
__PIC_JSR(_GET_PAGE_REG)
BEQ L_NOPAGE
PSHD
LDAA 0,X ;/* save page register */
MOVB 6,SP, 0,X ;/* set page register */
MOVW 2,SP, 0,Y ;/* store the value passed in X (high word) */
MOVW 0,SP, 2,Y ;/* store the value passed in D (low word) */
STAA 0,X ;/* restore page register */
PULD ;/* restore A register */
BRA done
L_NOPAGE:
MOVW 0,SP, 0,Y ;/* store the value passed in X (high word) */
STD 2,Y ;/* store the value passed in D (low word) */
done:
PULX ;/* restore X register */
MOVW 0,SP, 1,+SP ;/* move return address */
RTS
}
#else /* USE_SEVERAL_PAGES */
asm {
PSHD ;/* save D register */
LDAA PAGE_ADDR ;/* save page register */
LDAB 4,SP ;/* load page part of address */
STAB PAGE_ADDR ;/* set page register */
STX 0,Y ;/* store the value passed in X */
MOVW 0,SP, 2,Y ;/* store the value passed in D (low word) */
STAA PAGE_ADDR ;/* restore page register */
PULD ;/* restore D register */
MOVW 0,SP, 1,+SP ;/* move return address */
RTS
}
#endif /* USE_SEVERAL_PAGES */
}
/*--------------------------- _FAR_COPY_RC --------------------------------
This runtime routine is used to access paged memory via a runtime function.
It may also be used if the compiler option -Cp is not used with the runtime argument.
Arguments :
- offset part of the source int the X register
- page part of the source in the A register
- offset part of the dest int the Y register
- page part of the dest in the B register
- number of bytes to be copied is defined by the next 2 bytes after the return address.
Result :
- memory area copied
- no registers are saved, i.e. all registers may be destroyed
- all page register still contain the same value as before the call
- the function returns after the constant defining the number of bytes to be copied
stack-structure at the loop-label:
0,SP : destination offset
2,SP : source page
3,SP : destination page
4,SP : source offset
6,SP : points to length to be copied. This function returns after the size
A usual call to this function looks like:
struct Huge src, dest;
; ...
LDX #src
LDAA #PAGE(src)
LDY #dest
LDAB #PAGE(dest)
JSR _FAR_COPY_RC
DC.W sizeof(struct Huge)
; ...
--------------------------- _FAR_COPY_RC ----------------------------------*/
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _FAR_COPY_RC(void) {
#if USE_SEVERAL_PAGES
asm {
DEX ;/* source addr-=1, because loop counter ends at 1 */
PSHX ;/* save source offset */
PSHD ;/* save both pages */
DEY ;/* destination addr-=1, because loop counter ends at 1 */
PSHY ;/* save destination offset */
LDY 6,SP ;/* Load Return address */
LDX 2,Y+ ;/* Load Size to copy */
STY 6,SP ;/* Store adjusted return address */
loop:
LDD 4,SP ;/* load source offset */
LEAY D,X ;/* calculate actual source address */
LDAB 2,SP ;/* load source page */
__PIC_JSR(_LOAD_FAR_8) ;/* load 1 source byte */
PSHB ;/* save value */
LDD 0+1,SP ;/* load destination offset */
LEAY D,X ;/* calculate actual destination address */
PULA ;/* restore value */
LDAB 3,SP ;/* load destination page */
__PIC_JSR(_STORE_FAR_8) ;/* store one byte */
DEX
BNE loop
LEAS 6,SP ;/* release stack */
_SRET ;/* debug info only: This is the last instr of a function with a special return */
RTS ;/* return */
}
#else
asm {
PSHD ;/* store page registers */
TFR X,D
PSHY ;/* temporary space */
LDY 4,SP ;/* load return address */
ADDD 2,Y+ ;/* calculate source end address. Increment return address */
STY 4,SP
PULY
PSHD ;/* store src end address */
LDAB 2,SP ;/* reload source page */
LDAA PAGE_ADDR ;/* save page register */
PSHA
loop:
STAB PAGE_ADDR ;/* set source page */
LDAA 1,X+ ;/* load value */
MOVB 4,SP, PAGE_ADDR ;/* set destination page */
STAA 1,Y+
CPX 1,SP
BNE loop
LDAA 5,SP+ ;/* restore old page value and release stack */
STAA PAGE_ADDR ;/* store it into page register */
_SRET ;/* debug info only: This is the last instr of a function with a special return */
RTS
}
#endif
}
/*--------------------------- _FAR_COPY --------------------------------
The _FAR_COPY runtime routine was used to copied large memory blocks in previous compiler releases.
However this release now does use _FAR_COPY_RC instead. The only difference is how the size of
the area to be copied is passed into the function. For _FAR_COPY the size is passed on the stack just
above the return address. _FAR_COPY_RC does expect the return address just after the JSR _FAR_COPY_RC call
in the code of the caller. This allows for denser code calling _FAR_COPY_RC but does also need a slightly
larger runtime routine and it is slightly slower.
The _FAR_COPY routine is here now mainly for compatibility with previous releases.
The current compiler does not use it.
--------------------------- _FAR_COPY ----------------------------------*/
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _FAR_COPY(void) {
#if USE_SEVERAL_PAGES
asm {
DEX ;/* source addr-=1, because loop counter ends at 1 */
PSHX ;/* save source offset */
PSHD ;/* save both pages */
DEY ;/* destination addr-=1, because loop counter ends at 1 */
PSHY ;/* save destination offset */
LDX 8,SP ;/* load counter, assuming counter > 0 */
loop:
LDD 4,SP ;/* load source offset */
LEAY D,X ;/* calculate actual source address */
LDAB 2,SP ;/* load source page */
__PIC_JSR(_LOAD_FAR_8) ;/* load 1 source byte */
PSHB ;/* save value */
LDD 0+1,SP ;/* load destination offset */
LEAY D,X ;/* calculate actual destination address */
PULA ;/* restore value */
LDAB 3,SP ;/* load destination page */
__PIC_JSR(_STORE_FAR_8) ;/* store one byte */
DEX
BNE loop
LDX 6,SP ;/* load return address */
LEAS 10,SP ;/* release stack */
JMP 0,X ;/* return */
}
#else
asm {
PSHD ;/* store page registers */
TFR X,D
ADDD 4,SP ;/* calculate source end address */
STD 4,SP
PULB ;/* reload source page */
LDAA PAGE_ADDR ;/* save page register */
PSHA
loop:
STAB PAGE_ADDR ;/* set source page */
LDAA 1,X+ ;/* load value */
MOVB 1,SP, PAGE_ADDR ;/* set destination page */
STAA 1,Y+
CPX 4,SP
BNE loop
LDAA 2,SP+ ;/* restore old page value and release stack */
STAA PAGE_ADDR ;/* store it into page register */
LDX 4,SP+ ;/* release stack and load return address */
JMP 0,X ;/* return */
}
#endif
}
#else /* __HCS12X__ */
/*
The HCS12X knows two different kind of addresses:
- Logical addresses. E.g.
MOVB #page(var),RPAGE
INC var
- Global addresses E.g.
MOVB #page(var),GPAGE
GLDAA var
INCA
GSTAA var
Global addresses are used with G-Load's and G-Store's, logical addresses are used for all the other instructions
and occasions. As HC12's or HCS12's do not have the G-Load and G-Store instructions,
global addresses are not used with these processor families.
They are only used with HCS12X chips (and maybe future ones deriving from a HCS12X).
Logical and Global addresses can point to the same object, however the global and logical address of an object
are different for most objects (actually for all except the registers from 0 to 0x7FF).
Therefore the compiler needs to transform in between them.
HCS12X Pointer types:
The following are logical addresses:
- all 16 bit pointers
- "char* __near": always.
- "char *" in the small and banked memory model
- 24 bit dpage, epage, ppage or rpage pointers (*1) (note: the first HCS12X compilers may not support these pointer types)
- "char *__dpage": Note this type only exists for
orthogonality with the HC12 A4 chip which has a DPAGE reg.
It does not apply to the HCS12X.
- "char *__epage": 24 bit pointer using the EPAGE register
- "char *__ppage": 24 bit pointer using the PPAGE register.
As the PPAGE is also used for BANKED code,
using this pointer type is only legal from non banked code.
- "char *__rpage": 24 bit pointer using the RPAGE register
The following are global addresses:
"char*": in the large memory model (only HCS12X)
"char* __far": always for HCS12X.
(*1): For the HC12 and HCS12 "char* __far" and "char*" in the large memory model are also logical.
Some notes for the HC12/HCS12 programmers.
The address of a far object for a HC12 and for a HCS12X is different, even if they are at the same place in the memory map.
For the HC12, a far address is using the logical addresses, for the HCS12X however, far addresses are using global addresses.
This does cause troubles for the unaware!

The conversion routines implemented in this file support the special HCS12XE RAM mapping (when RAMHM is set).
To enable this mapping compile this file with the "-MapRAM" compiler option.
HCS12X Logical Memory map
Logical Addresses Used for shadowed at page register Global Address
0x000000 .. 0x0007FF Peripheral Registers Not Paged 0x000000
0x??0800 .. 0x??0BFF Paged EEPROM EPAGE (@0x17) 0x100000+EPAGE*0x0400
0x000C00 .. 0x000FFF Non Paged EEPROM 0xFF0800..0xFF0FFF Not Paged 0x13FC00
0x??1000 .. 0x??1FFF Paged RAM RPAGE (@0x16) 0x000000+RPAGE*0x1000
0x002000 .. 0x003FFF Non Paged RAM 0xFE1000..0xFF1FFF Not Paged 0x0FE000
0x004000 .. 0x007FFF Non Paged FLASH 0xFC8000..0xFCBFFF Not Paged 0x7F4000
0x??8000 .. 0x00BFFF Paged FLASH PPAGE (@0x30) 0x400000+PPAGE*0x4000
0x00C000 .. 0x00FFFF Non Paged FLASH 0xFF8000..0xFFBFFF Not Paged 0x7FC000
NA: Not Applicable
HCS12X Global Memory map
Global Addresses Used for Logical mapped at
0x000000 .. 0x0007FF Peripheral Registers 0x000000 .. 0x0007FF
0x000800 .. 0x000FFF DMA registers Not mapped
0x001000 .. 0x0FFFFF RAM 0x??1000 .. 0x??1FFF
0x0FE000 .. 0x0FFFFF RAM, Log non paged 0x002000 .. 0x003FFF
0x100000 .. 0x13FFFF EEPROM 0x??0800 .. 0x??0BFF
0x13FC00 .. 0x13FFFF EEPROM non paged 0x000C00 .. 0x000FFF
0x140000 .. 0x3FFFFF External Space Not mapped
0x400000 .. 0x7FFFFF FLASH 0x??8000 .. 0x??BFFF
0x7F4000 .. 0x7F7FFF FLASH, Log non paged 0x004000 .. 0x007FFF
0x7FC000 .. 0x7FFFFF FLASH, Log non paged 0x00C000 .. 0x00FFFF
HCS12XE Logical Memory map (with RAMHM set)
Logical Addresses Used for shadowed at page register Global Address
0x000000 .. 0x0007FF Peripheral Registers Not Paged 0x000000
0x??0800 .. 0x??0BFF Paged EEPROM EPAGE 0x100000+EPAGE*0x0400
0x000C00 .. 0x000FFF Non Paged EEPROM 0xFF0800..0xFF0FFF Not Paged 0x13FC00
0x??1000 .. 0x??1FFF Paged RAM RPAGE 0x000000+RPAGE*0x1000
0x002000 .. 0x003FFF Non Paged RAM 0xFA1000..0xFB1FFF Not Paged 0x0FA000
0x004000 .. 0x007FFF Non Paged RAM 0xFC1000..0xFF1FFF Not Paged 0x0FC000
0x??8000 .. 0x00BFFF Paged FLASH PPAGE 0x400000+PPAGE*0x4000
0x00C000 .. 0x00FFFF Non Paged FLASH 0xFF8000..0xFFBFFF Not Paged 0x7FC000
NA: Not Applicable
HCS12X Global Memory map (with RAMHM set)
Global Addresses Used for Logical mapped at
0x000000 .. 0x0007FF Peripheral Registers 0x000000 .. 0x0007FF
0x000800 .. 0x000FFF DMA registers Not mapped
0x001000 .. 0x0FFFFF RAM 0x??1000 .. 0x??1FFF
0x0FA000 .. 0x0FFFFF RAM, Log non paged 0x002000 .. 0x007FFF
0x100000 .. 0x13FFFF EEPROM 0x??0800 .. 0x??0BFF
0x13FC00 .. 0x13FFFF EEPROM non paged 0x000C00 .. 0x000FFF
0x140000 .. 0x3FFFFF External Space Not mapped
0x400000 .. 0x7FFFFF FLASH 0x??8000 .. 0x??BFFF
0x7F4000 .. 0x7F7FFF FLASH, Log non paged Not mapped
0x7FC000 .. 0x7FFFFF FLASH, Log non paged 0x00C000 .. 0x00FFFF
How to read this table:
For logical addresses, the lower 16 bits of the address do determine in which area the address is,
if this address is paged, then this entry also controls and which of the EPAGE, PPAGE or RPAGE
page register is controlling the bits 16 to 23 of the address.
For global addresses, the bits 16 to 23 have to be in the GPAGE register and the lower 16 bits
have to be used with the special G load or store instructions (e.g. GLDAA).
As example the logical address 0x123456 is invalid. Because its lower bits 0x3456 are in a
non paged area, so the page 0x12 does not exist.
The address 0xFE1020 however does exist. To access it, the RPAGE has to contain 0xFE and the
offset 0x1020 has to be used.
ORG $7000
MOVB #0xFE, 0x16 ; RPAGE
LDAA 0x1020 ; reads at the logical address 0xFE1020
Because the last two RAM pages are also accessible directly from 0x2000 to 0x3FFF, the
following shorter code does read the same memory location:
ORG $7000
LDAA 0x2020 ; reads at the logical address 0x2020
; which maps to the same memory as 0xFE1020
This memory location also has a global address. For logical 0xFE1020 the global address is 0x0FE020.
So the following code does once more access the same memory location:
ORG $7000
MOVB #0x0F, 0x10 ; GPAGE
GLDAA 0xE020 ; reads at the global address 0x0FE020
; which maps to the same memory as the logical addr. 0xFE1020
Therefore every memory location for the HCS12X has up to 3 different addresses.
Up to two logical and one global.
Notes.
- Not every address has a logical equivalent. The external space is only available in the global address space.
- The PPAGE must only be set if the code is outside of the 0x8000 to 0xBFFF range.
If not, the next code fetch will be from the new wrong PPAGE value.
- Inside of the paged area, the highest pages are allocated first. So all HCS12X's do have the FF pages
(if they have this memory type at all).
- For RPAGE, the value 0 is illegal. Otherwise the global addresses would overlap with the registers.
*/
/*lint -e10, -e106, -e30 */
#if __OPTION_ACTIVE__("-MapRAM")
#define __HCS12XE_RAMHM_SET__
#endif
/*lint +e10, +e106, +e30 */
/*--------------------------- pointer conversion operations -------------------------------*/
/*--------------------------- _CONV_GLOBAL_TO_LOGICAL --------------------------------
Convert 24 bit logical to 24 bit global pointer
("char*__far" to "char*__gpage")
Arguments :
- B : page part of global address
- X : 16 offset part of global address
Postcondition :
- B == page of returned logical address
- X == offset of returned logical address
- Y remains unchanged
- A remains unchanged
*/
/*--------------------------- Convert 24 bit global to 24 bit logical pointer ----------------------------------*/
/* B:X = Logical(B:X) */
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_FRAME
#pragma NO_ENTRY
#pragma NO_EXIT
void NEAR _CONV_GLOBAL_TO_LOGICAL(void) {
asm {
CMPB #0x40 ;/* flash (0x400000..0x7FFFFF) or not? */
BLO Below400000
/* from 0x400000 to 0x7FFFFF */
CMPB #0x7F ;/* check for Unpaged areas 0x7FC000..0x7FFFFF and 0x7F4000..0x7F7FFF */
BNE PAGED_FLASH_AREA
#ifndef __HCS12XE_RAMHM_SET__
BITX #0x4000
BEQ PAGED_FLASH_AREA
#else
CPX #0xC000
BLO PAGED_FLASH_AREA
#endif
/* from 0x7F4000 to 0x7F7FFF or 0x7FC000 to 0x7FFFFF */
;/* Note: offset in X is already OK. */
CLRB ;/* logical page == 0 */
RTS
PAGED_FLASH_AREA: ;/* paged flash. Map to 0x8000..0xBFFF */
/* from 0x400000 to 0x7F3FFF or 0x7F8000 to 0x7FBFFF */
LSLX ; /* shift 24 bit address 2 bits to the left to get correct page in B */
ROLB
LSLX
ROLB
LSRX ; /* shift back to get offset from 0x8000 to 0xBFFF */
SEC
RORX
RTS ;/* done */
Below400000:
/* from 0x000000 to 0x3FFFFF */
#if 0 /* How should we handle mapping to External Space. There is no logical equivalent. This is an error case! */
CMPB #0x14 ;/* check if above 0x140000. If so, its in the external space */
BLO Below140000
ERROR !!!! ;/* this mapping is not possible! What should we do? */
RTS
Below140000:
/* from 0x000000 to 0x13FFFF */
#endif
CMPB #0x10 ;/* if >= 0x100000 it's EEPROM */
BLO Below100000
/* from 0x100000 to 0x13FFFF (or 0x3FFFFF) */
CMPB #0x13 ;/* check if its is in the non paged EEPROM area at 0x13FC00..0x13FFFF */
BLO Below13FC00
CPX #0xFC00
BLO Below13FC00
/* from 0x13FC00 to 0x13FFFF (or 0x3FFFFF) */
LEAX 0x1000,X ;/* same as SUBX #0xF000 // map from 0xFC00 to 0x0C00 */
CLRB
RTS
Below13FC00:
/* from 0x100000 to 0x13FBFF */
PSHA
TFR XH,A ;/* calculate logical page */
EXG A,B
LSRD
LSRD
PULA
ANDX #0x03FF
LEAX 0x0800,X ;/* same as ORX #0x0800 */
RTS
Below100000:
/* from 0x000000 to 0x0FFFFF */
TSTB
BNE RAM_AREA
CPX #0x1000
BLO Below001000
RAM_AREA:
/* from 0x001000 to 0x0FFFFF */
CMPB #0x0F
BNE PagedRAM_AREA
#ifndef __HCS12XE_RAMHM_SET__
CPX #0xE000
BLO PagedRAM_AREA
/* from 0x0FE000 to 0x0FFFFF */
SUBX #(0xE000-0x2000) ;/* map 0xE000 to 0x2000 */
#else
CPX #0xA000
BLO PagedRAM_AREA
/* from 0x0FA000 to 0x0FFFFF */
SUBX #(0xA000-0x2000) ;/* map 0xA000 to 0x2000 */
#endif
CLRB ;/* Page is 0 */
RTS
PagedRAM_AREA:
/* from 0x001000 to 0x0FDFFF */
PSHA
TFR XH, A ;/* calculate logical page */
EXG A,B
LSRD
LSRD
LSRD
LSRD
PULA
ANDX #0x0FFF
LEAX 0x1000,X ;/* same as ORX #0x1000 */
RTS
Below001000:
/* from 0x000000 to 0x000FFF */
#if 0
CMPA #0x08
BLO Below000800
/* from 0x000800 to 0x000FFF */
/* ??? DMA Regs? */
RTS
Below000800:
/* from 0x000000 to 0x0007FF */
#endif
CLRB
RTS
}
}
/*--------------------------- _CONV_GLOBAL_TO_NEAR --------------------------------
Convert 24 bit global to 16 bit logical pointer
("char*__far" to "char*")
Arguments :
- B : page part of global address
- X : 16 offset part of global address
Postcondition :
- B is undefined
- A remains unchanged
- X == offset of returned logical address
- Y remains unchanged
*/
/*--------------------------- Convert 24 bit global to 16 bit logical pointer ----------------------------------*/
/* X = Logical(B:X) */
#ifdef __cplusplus
extern "C"
#endif
#define _REUSE_CONV_GLOBAL_TO_LOGICAL 1
#pragma NO_FRAME
#pragma NO_ENTRY
#pragma NO_EXIT
void NEAR _CONV_GLOBAL_TO_NEAR(void){
#if _REUSE_CONV_GLOBAL_TO_LOGICAL /* do we want an optimized version? */
__asm JMP _CONV_GLOBAL_TO_LOGICAL; /* offset for NEAR is same as for LOGICAL. */
#else
asm {
CMPB #0x40 ;/* flash (0x400000..0x7FFFFF) or not? */
BLO Below400000
/* from 0x400000 to 0x7FFFFF */
#ifndef __HCS12XE_RAMHM_SET__
CMPB #0x7F ;/* check for Unpaged areas 0x7FC000..0x7FFFFF and 0x7F4000..0x7F7FFF */
BNE PAGED_FLASH_AREA
CPX #0x4000
BLO PAGED_FLASH_AREA
/* from 0x7F4000 to 0x7FFFFF */
#else
CMPB #0x7F ;/* check for Unpaged area 0x7FC000..0x7FFFFF */
BNE PAGED_FLASH_AREA
CPX #0xC000
BLO PAGED_FLASH_AREA
/* from 0x7FC000 to 0x7FFFFF */
#endif
;/* note non PAGED flash areas or paged area 0x7F8000..0x7FBFFF which are mapping all correctly */
RTS
PAGED_FLASH_AREA: ;/* paged flash. Map to 0x8000..0xBFFF */
/* from 0x400000 to 0x7F3FFF */
ANDX #0x3F00 ;/* cut to 0.. 0x3FFF */
LEAX 0x8000,X ;/* same as ORX #0x8000 ;// move to 0x8000..0xBFFF */
RTS ;/* done */
Below400000:
/* from 0x000000 to 0x3FFFFF */
#if 0 /* How should we handle mapping to External Space. There is no logical equivalent. This is an error case! */
CMPB #0x14 ;/* check if above 0x140000. If so, its in the external space */
BLO Below140000
ERROR !!!! ;/* this mapping is not possible! What should we do? */
RTS
Below140000:
/* from 0x000000 to 0x13FFFF */
#endif
CMPB #0x10 ;/* if >= 0x100000 it's EEPROM */
BLO Below100000
/* from 0x100000 to 0x13FFFF (or 0x3FFFFF) */
CMPB #0x13 ;/* check if its is in the non paged EEPROM area at 0x13FC00..0x13FFFF */
BNE Below13FC00
CPX #0xFC00
BLO Below13FC00
/* from 0x13FC00 to 0x13FFFF (or 0x3FFFFF) */
SUBX #0xF000 ;/* map from 0xFC00 to 0x0C00 */
RTS
Below13FC00:
/* from 0x100000 to 0x13FBFF */
ANDX #0x03FF
LEAX 0x800,X ;/* same as ORX #0x0800 */
RTS
Below100000:
/* from 0x000000 to 0x0FFFFF */
TBNE B,RAM_AREA
CPX #0x1000
BLO Below001000
RAM_AREA:
/* from 0x001000 to 0x0FFFFF */
CMPB #0x0F
BNE PagedRAM_AREA
#ifndef __HCS12XE_RAMHM_SET__
CPX #0xE000
BLO PagedRAM_AREA
/* from 0x0FE000 to 0x0FFFFF */
SUBX #(0xE000-0x2000) ;/* map 0xE000 to 0x2000 */
#else
CPX #0xA000
BLO PagedRAM_AREA
/* from 0x0FA000 to 0x0FFFFF */
SUBX #(0xA000-0x2000) ;/* map 0xA000 to 0x2000 */
#endif
RTS
PagedRAM_AREA:
/* from 0x001000 to 0x0FDFFF (0x001000 to 0x0F9FFF if HCS12XE RAM mapping is enabled) */
ANDX #0x0FFF
LEAX 0x1000,X ;/* same as ORX #0x1000 */
RTS
Below001000:
/* from 0x000000 to 0x000FFF */
RTS
}
#endif
}
/*--------------------------- _CONV_NEAR_TO_GLOBAL --------------------------------
Convert 16 bit logical to 24 bit global pointer
("char*__near" to "char*__far")
Arguments :
- X : 16 bit near pointer
Postcondition :
- B == page of returned global address
- X == offset of returned global address
- Y remains unchanged
- A is unspecified
*/
/*--------------------------- Convert 16 bit logical to 24 bit global pointer ----------------------------------*/
/* B:X = Global(X) */
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_FRAME
#pragma NO_ENTRY
#pragma NO_EXIT
void NEAR _CONV_NEAR_TO_GLOBAL(void){
asm {
/* syntax: */
/* input 16 bit offset is bit15..bit0 */
/* ppage values: ppage7..ppage0 */
/* epage values: epage7..epage0 */
/* dpage values: dpage7..dpage0 */
/* rpage values: rpage7..rpage0 */
PSHX ;/* D contains bit15..bit0 */
TFR X,D ;/* D is cheaper to shift */
LSLD ;/* D contains 0 bit14..bit0, C contains bit15 */
BCC Below8000 ;/* bit15 == 0? */
/* from 0x8000 to 0xFFFF */
LSLD ;/* D contains 00 bit13..bit0, C contains bit14 */
BCC BelowC000
LDAB #0x7F
PULX
RTS ;/* returns 0b0111 1111 11 bit13...bit0 */
BelowC000: ;/* from 0x8000 to 0xBFFF */
TFR D,X
LDAB __PPAGE_ADR__
SEC
RORB
RORX
LSRB
RORX
LEAS 2,SP
RTS ;/* returns 0b01 ppage7..ppage0 bit13...bit0 */
Below8000:
LSLD ;/* D contains 00 bit13..bit0, C contains bit14 */
BCC Below4000
/* from 0x4000 to 0x7FFF */
PULX
#ifndef __HCS12XE_RAMHM_SET__
LDAB #0x7F
#else
LEAX (0xC000-0x4000),X
LDAB #0x0F
#endif
RTS ;/* returns 0b0111 1111 01 bit13...bit0 */
Below4000:
LSLD ;/* D contains 000 bit12..bit0, C contains bit13 */
BCC Below2000
/* from 0x2000 to 0x3FFF */
PULX
#ifndef __HCS12XE_RAMHM_SET__
LEAX (0xE000-0x2000),X
#else
LEAX (0xA000-0x2000),X
#endif
LDAB #0x0F
RTS ;/* returns 0b0000 1111 111 bit12...bit0 */
Below2000:
LSLD ;/* D contains 0000 bit11..bit0, C contains bit12 */
BCC Below1000
/* from 0x1000 to 0x1FFF */
LDAB __RPAGE_ADR__
LDAA #0x10
MUL
EORB 0,SP
EORB #0x10 ;/* clear 1 bit */
STAB 0,SP
TFR A,B
PULX
RTS
Below1000:
LSLD ;/* D contains 0000 0 bit10..bit0, C contains bit11 */
BCC Below0800
/* from 0x0800 to 0x0FFF */
LSLD ;/* D contains 0000 00 bit9..bit0, C contains bit10 */
BCC Below0C00
/* from 0x0C00 to 0x0FFF */
LDAB #0x13
PULX
LEAX 0xF000,X
RTS ;/* returns 0b0001 0011 1111 11 bit9...bit0 */
Below0C00:
/* from 0x0800 to 0x0BFF */
LDAB __EPAGE_ADR__
LDAA #0x04
MUL
EORB 0,SP
EORB #0x08
STAB 0,SP
TFR A,B
ORAB #0b00010000
PULX
RTS
Below0800:
PULX
CLRB
RTS
}
}
/*--------------------------- _CONV_STACK_NEAR_TO_GLOBAL --------------------------------
Convert 16 bit logical of address on the stack 24 bit global pointer
("char*__near" to "char*__far")
Arguments :
- X : 16 bit near pointer
Postcondition :
- B == page of returned global address
- X == offset of returned global address
- Y remains unchanged
- A is unspecified
*/
/*--------------------------- Convert 16 bit logical stack address to 24 bit global pointer ----------------------------------*/
/* B:X = Global(D) */
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_FRAME
#pragma NO_ENTRY
#pragma NO_EXIT
void NEAR _CONV_STACK_NEAR_TO_GLOBAL(void){
asm {
/* syntax: */
/* input 16 bit offset is bit15..bit0 */
/* ppage values: ppage7..ppage0 */
/* epage values: epage7..epage0 */
/* dpage values: dpage7..dpage0 */
/* rpage values: rpage7..rpage0 */
/* stack must be between $1000 and $3FFF. */
/* actually placing the stack at $1000 implies that the RPAGE register is not set (and correctly initialized) */
CPX #0x2000
BLO PAGED_RAM
/* Map 0x2000 to 0x0FE000 (0x0FA000 for HCS12XE RAM mapping is enabled) */
LDAB #0x0F
#ifndef __HCS12XE_RAMHM_SET__
LEAX (0xE000-0x2000),X ;/* LEAX is one cycle faster than ADDX # */
#else
LEAX (0xA000-0x2000),X ;/* LEAX is one cycle faster than ADDX # */
#endif
RTS
PAGED_RAM:
PSHX
LDAB __RPAGE_ADR__
LDAA #0x20
MUL
EORB 0,SP
EORB #0x10 ;/* clear 1 bit */
STAB 0,SP
TFR A,B
PULX
RTS
}
}
/*--------------------------- _CONV_LOGICAL_TO_GLOBAL --------------------------------
Convert 24 bit global to 24 bit logical pointer
("char*__far" to "char*__gpage")
Arguments :
- B : page part of logical address
- X : 16 offset part of logical address
Postcondition :
- B == page of returned global address
- X == offset of returned global address
- Y remains unchanged
- A remains unchanged
*/
/*--------------------------- Convert 24 bit logical to 24 bit global pointer ----------------------------------*/
/* B:X = Logical(B:X) */
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_FRAME
#pragma NO_ENTRY
#pragma NO_EXIT
void NEAR _CONV_LOGICAL_TO_GLOBAL(void) {
asm {
/* syntax: */
/* input 16 bit offset is bit15..bit0 */
/* ppage values: ppage7..ppage0 */
/* epage values: epage7..epage0 */
/* dpage values: dpage7..dpage0 */
/* rpage values: rpage7..rpage0 */
PSHA ;/* save A across this routine. */
PSHX ;/* D contains bit15..bit0 */
PSHB ;/* store page */
TFR X,D ;/* D is cheaper to shift */
LSLD ;/* D contains 0 bit14..bit0, C contains bit15 */
BCC Below8000 ;/* bit15 == 0? */
/* from 0x8000 to 0xFFFF */
LSLD ;/* D contains 00 bit13..bit0, C contains bit14 */
BCC BelowC000
PULB ;/* cleanup stack */
LDAB #0x7F
PULX
PULA
RTS ;/* returns 0b0111 1111 11 bit13...bit0 */
BelowC000: ;/* from 0x8000 to 0xBFFF */
TFR D,X
PULB ;/* cleanup stack */
SEC
RORB
RORX
LSRB
RORX
LEAS 2,SP
PULA
RTS ;/* returns 0b01 ppage7..ppage0 bit13...bit0 */
Below8000:
LSLD ;/* D contains 00 bit13..bit0, C contains bit14 */
BCC Below4000
;/* from 0x4000 to 0x7FFF */
PULB ;/* cleanup stack */
PULX
#ifndef __HCS12XE_RAMHM_SET__
LDAB #0x7F
#else
LEAX (0xC000-0x4000),X
LDAB #0x0F
#endif
PULA
RTS ;/* returns 0b0111 1111 01 bit13...bit0 */
Below4000:
LSLD ;/* D contains 000 bit12..bit0, C contains bit13 */
BCC Below2000
/* from 0x2000 to 0x3FFF */
PULB ;/* cleanup stack */
PULX
#ifndef __HCS12XE_RAMHM_SET__
LEAX (0xE000-0x2000),X
#else
LEAX (0xA000-0x2000),X
#endif
LDAB #0x0F
PULA
RTS ;/* returns 0b0000 1111 111 bit12...bit0 */
Below2000:
LSLD ;/* D contains 0000 bit11..bit0, C contains bit12 */
BCC Below1000
/* from 0x1000 to 0x1FFF */
PULB
LDAA #0x10
MUL
EORB 0,SP
EORB #0x10 ;/* clear 1 bit */
STAB 0,SP
TFR A,B
PULX
PULA
RTS
Below1000:
LSLD ;/* D contains 0000 0 bit10..bit0, C contains bit11 */
BCC Below0800
/* from 0x0800 to 0x0FFF */
LSLD ;/* D contains 0000 00 bit9..bit0, C contains bit10 */
BCC Below0C00
/* from 0x0C00 to 0x0FFF */
PULB ;/* cleanup stack */
LDAB #0x13
PULX
LEAX 0xF000,X
PULA
RTS ;/* returns 0b0001 0011 1111 11 bit9...bit0 */
Below0C00:
/* from 0x0800 to 0x0BFF */
PULB
LDAA #0x04
MUL
EORB 0,SP
EORB #0x08
STAB 0,SP
TFR A,B
ORAB #0b00010000
PULX
PULA
RTS
Below0800:
PULB
PULX
PULA
CLRB
RTS
}
}
/*--------------------------- _FAR_COPY_RC HCS12X Routines --------------------------------
copy larger far memory blocks
There are the following memory block copy routines:
_COPY : 16 bit logical copies.
Src and dest are both near. Note: implemented in rtshc12.c and not here.
_FAR_COPY_RC HC12/HCS12 struct copy routine.
Expects HC12/HCS12 logical 24 bit address.
Note: Does not exist for the HCS12X.
The HC12/HCS12 implementation is implemented above.
_FAR_COPY_GLOBAL_GLOBAL_RC:
_FAR_COPY_GLOBAL_LOGICAL_RC:
_FAR_COPY_LOGICAL_GLOBAL_RC:
_FAR_COPY_LOGICAL_LOGICAL_RC:
_FAR_COPY_NEAR_GLOBAL_RC:
_FAR_COPY_NEAR_LOGICAL_RC:
_FAR_COPY_GLOBAL_NEAR_RC:
_FAR_COPY_LOGICAL_NEAR_RC: HCS12X specific far copy routine. The name describes what the src/dest address format are.
All near src arguments are passed in X, all 24 bit src in X/B.
All near dest arguments are passed in Y, all 24 bit src in Y/A.
(Note: HC12 _FAR_COPY_RC is using X/A as src and Y/B as dest, so the register usage is not the same!)
Arguments :
- B:X : src address (for NEAR/_COPY: only X)
- A:Y : dest address (for NEAR/_COPY: only Y)
- number of bytes to be copied behind return address (for _COPY: in D register). The number of bytes is always > 0
Result :
- memory area copied
- no registers are saved, i.e. all registers may be destroyed
- for _COPY: D contains 0.
- for HCS12X _FAR_COPY_... routines: GPAGE state is unknown
*/
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _FAR_COPY_GLOBAL_GLOBAL_RC(void) {
asm {
PSHD
PSHY
LDY 4,SP ;/* load return address */
LDD 2,Y+ ;/* load size */
STY 4,SP ;/* store return address */
PULY
PSHD
LDAB 3,SP
Loop:
STAB __GPAGE_ADR__
GLDAA 1,X+
MOVB 2,SP,__GPAGE_ADR__
GSTAA 1,Y+
DECW 0,SP
BNE Loop
LEAS 4,SP
_SRET ;/* debug info only: This is the last instr of a function with a special return */
RTS
}
}
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _SET_PAGE_REG_HCS12X(void) {
/* Sets the page contained in A to the register controlling the logical addr contained in X. */
/* saves the old page before and returns it in A together with the page address just below the return address. */
/* X/Y both remain valid. */
asm {
PSHX
/* 0000..FFFF */
CPX #0x8000
BLO _LO8000
LDX #__PPAGE_ADR__
BRA Handle
_LO8000:
/* 0000..7FFF */
CPX #0x1000
BLO _LO1000
LDX #__RPAGE_ADR__
BRA Handle
_LO1000:
LDX #__EPAGE_ADR__
Handle:
LDAA 0,X ;/* load old page register content */
STAB 0,X ;/* set new page register */
STX 4,SP
PULX
RTS
}
}
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _FAR_COPY_GLOBAL_LOGICAL_RC(void) {
asm {
STAB __GPAGE_ADR__
EXG X,Y
TFR A,B
PSHY ;/* space to store size */
PSHX ;/* allocate some space where _SET_PAGE_REG_HCS12X can return the page */
LDY 4,SP ;/* load return address */
LDX 2,Y+ ;/* load size */
STY 4,SP
LDY 2,SP ;/* restore dest pointer */
STX 2,SP ;/* store size */
LDX 0,SP ;/* reload src pointer */
__PIC_JSR(_SET_PAGE_REG_HCS12X)
Loop: GLDAB 1,Y+
STAB 1,X+
DECW 2,SP
BNE Loop
PULX ;/* reload page register address */
STAA 0,X ;/* restore old page content (necessary if it was PPAGE) */
PULX ;/* clean up stack */
_SRET ;/* debug info only: This is the last instr of a function with a special return */
RTS
}
}
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _FAR_COPY_LOGICAL_GLOBAL_RC(void) {
asm {
STAA __GPAGE_ADR__
PSHY ;/* space to store size */
PSHX ;/* allocate some space where _SET_PAGE_REG_HCS12X can return the page */
LDY 4,SP ;/* load return address */
LDX 2,Y+ ;/* load size */
STY 4,SP
LDY 2,SP ;/* restore dest pointer */
STX 2,SP ;/* store size */
LDX 0,SP ;/* reload src pointer */
__PIC_JSR(_SET_PAGE_REG_HCS12X)
Loop: LDAB 1,X+
GSTAB 1,Y+
DECW 2,SP
BNE Loop
PULX
STAA 0,X ;/* restore old page content (necessary if it was PPAGE) */
PULX ;/* clean up stack */
_SRET ;/* debug info only: This is the last instr of a function with a special return */
RTS
}
}
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _FAR_COPY_LOGICAL_LOGICAL_RC(void) {
asm {
PSHA
__PIC_JSR(_CONV_LOGICAL_TO_GLOBAL);
PULA
__PIC_JMP(_FAR_COPY_GLOBAL_LOGICAL_RC);
}
}
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _FAR_COPY_NEAR_GLOBAL_RC(void) {
asm {
CLRB
__PIC_JMP(_FAR_COPY_LOGICAL_GLOBAL_RC);
}
}
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _FAR_COPY_NEAR_LOGICAL_RC(void) {
asm {
PSHA
__PIC_JSR(_CONV_NEAR_TO_GLOBAL);
PULA
__PIC_JMP(_FAR_COPY_GLOBAL_LOGICAL_RC);
}
}
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _FAR_COPY_GLOBAL_NEAR_RC(void) {
asm {
CLRA /* near to logical (we may have to use another runtime if this gets non trivial as well :-( */
__PIC_JMP(_FAR_COPY_GLOBAL_LOGICAL_RC);
}
}
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _FAR_COPY_LOGICAL_NEAR_RC(void) {
asm {
EXG A,B
EXG X,Y
PSHA
__PIC_JSR(_CONV_NEAR_TO_GLOBAL);
PULA
EXG A,B
EXG X,Y
__PIC_JMP(_FAR_COPY_LOGICAL_GLOBAL_RC);
}
}
/* _FAR_COPY_LOGICAL_GLOBAL: is used by some old wizard generated projects. Not used by current setup anymore */
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
void NEAR _FAR_COPY_LOGICAL_GLOBAL(void) {
asm {
STAA __GPAGE_ADR__
PSHX ;/* allocate some space where _SET_PAGE_REG_HCS12X can return the page */
__PIC_JSR(_SET_PAGE_REG_HCS12X)
Loop: LDAB 1,X+
GSTAB 1,Y+
DECW 4,SP
BNE Loop
PULX
STAA 0,X ;/* restore old page content (necessary if it was PPAGE) */
LDX 4,SP+ ;/* load return address and clean stack */
JMP 0,X
}
}
#endif /* __HCS12X__ */
/*----------------- end of code ------------------------------------------------*/
/*lint --e{766} , runtime.sgm is not a regular header file, it contains a conditionally compiled CODE_SEG pragma */
dip_switch_c/Sources/derivative.h
/*
* Note: This file is recreated by the project wizard whenever the MCU is
* changed and should not be edited by hand
*/
/* Include the derivative-specific header file */
#include
#pragma LINK_INFO DERIVATIVE "mc9s12c32"
dip_switch_c/Sources/main.c
#include /* common defines and macros */
#include...
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