The Poisson arrival rate of a soft error strike on a single bit of an SRAM cell in a single cycle is λ = 10−25. Assume a cache of only one word and that the data are brought into the cache during the first cycle of program execution. We also assume that soft errors strike only the cache and no other processor structures.
(a) What is the probability of having a single bit fault in the cache during the execution of a program that runs for one billion cycles, assuming that the cache word is vulnerable all through the billion cycles of program execution? If a cycle is 1 ns, what is the FIT rate (and also the MTTF in years) of this cache? Note that the FIT value computed here is called the intrinsic FIT rate.
(b) Now consider the case that after every one million cycles the cache word is overwritten by the processor with new data. In this case what is the FIT rate of this cache? Note that when data are overwritten the new value has just entered the cache, and hence any soft error strikes on the old value are irrelevant.
(c) Now consider the case that the cache is protected by a single bit parity. Compute the DUE and SDC FIT rate for this cache.
(d) Now consider the case that the cache is protected by a single error correcting double error detecting (SECDED) code. Compute the DUE and SDC FIT rate for this SECDED cache.
(e) Now consider the case that the soft error strikes flip two bits in the same word with a 30% chance. That is, 70% of the soft error strikes flip only one bit and 30% of them flip two bits in the same word simultaneously. Compare the DUE and SDC FIT rate for the cache when the cache is protected by a single bit odd parity and when the cache is protected by a SECDED code.