The nFET of Fig. P3.34 has Vt 5 0.5 V, k 5 0.5 mA/V2 , and 5 0. Moreover, VDD 5 2VSS 5 5 V. (a) Specify RD and RS to bias the FET at ID 5 1 mA and VDS 5 3 V. (b) Repeat, but for VDS 5 1 V. (c) What...

The nFET of Fig. P3.34 has Vt 5 0.5 V, k 5 0.5 mA/V2 , and 5 0. Moreover, VDD 5 2VSS 5 5 V. (a) Specify RD and RS to bias the FET at ID 5 1 mA and VDS 5 3 V. (b) Repeat, but for VDS 5 1 V. (c) What happens if RD is set to 0 (shorted out) in part (b)? What is the new operating point of the FET?