The following truth table needs to be implemented using two-input NAND gates and inverters. TNAND (two-input NAND gate delay) = 500 ps TINV (inverter delay) = 500 ps tclk-q (clock-to-q delay) = 200 ps...

The following truth table needs to be implemented using two-input NAND gates and inverters.

TNAND (two-input NAND gate delay) = 500 ps

TINV (inverter delay) = 500 ps

tclk-q (clock-to-q delay) = 200 ps

tsu (setup time) = 200 ps

th (hold time) = 300 ps

(a) Implement this truth table between two flip-flop boundaries.

(b) Find the maximum clock frequency using a timing diagram.

(c) Shift the clock by 500 ps at the receiving flip-flop boundary. Show whether or not there is a hold violation using a timing diagram.