The following table shows the contents of a 4-entry TLB. Entry-ID Valid VA Page Modified Protection PA Page 1 2 3 4 1 0 1 1 140 40 200 280 1 0 1 0 RW RX RO RW 30 34 32 31 Under what scenarios would...

The following table shows the contents of a 4-entry TLB.

Under what scenarios would entry 2’s valid bit be set to zero?
What happens when an instruction writes to VA page 30? When would a soft ware managed TLB be faster than a hardware managed TLB?
What happens when an instruction writes to VA page 200?