The following instruction set needs to be executed in a 32-bit RISC CPU organized in Little Endian format. The CPU has three pipeline stages where the ALU and write-back stages are combined. The CPU...

The following instruction set needs to be executed in a 32-bit RISC CPU organized in Little Endian format. The CPU has three pipeline stages where the ALU and write-back stages are combined. The CPU is capable of executing the integer (ADDI, SLI and SRI) and floating-point (ADDF and MULF) instructions. The CPU stores the fixed and floating-point numbers in two separate register files, each containing 32 registers. In the instruction set below, RS and RD are defined as the source and the destination addresses for the fixed-point registers. Similarly, FS1, FS2 and FD are the source and the destination addresses for the floating-point registers. Show a detailed data-path of this CPU, indicating all internal bus widths and port names. Include only the necessary functional units.