The FET of Fig. P3.43 has Vt 5 21.0 V, k 5 0.75 mA/V2 , and 5 0. (a) Assuming VDD 5 28 V, specify suitable resistance values to bias the device at ID 5 1.5 mA with VD half-way between the values...

The FET of Fig. P3.43 has Vt 5 21.0 V, k 5 0.75 mA/V2 , and 5 0. (a) Assuming VDD 5 28 V, specify suitable resistance values to bias the device at ID 5 1.5 mA with VD half-way between the values corresponding to the edge of conduction and the edge of saturation; specify R1 and R2 in the MV range. (b) How is the FET’s operating point Q affected if VDD is changed to 25 V? (c) To 21.5 V?