The estimated average memory latency in Example 10.1 is computed for peak performance. Suppose in the worst-case scenario none of the request and response transactions can be overlapped. Recalculate...

The estimated average memory latency in Example 10.1 is computed for peak performance. Suppose in the worst-case scenario none of the request and response transactions can be overlapped. Recalculate the estimated average memory latency, assuming that every SDRAM access (from the time a row address is issued until the first data item appears on the bus) takes five SDRAM clock cycles. Ignore the time required to deactivate a row.