The differential pair circuit shown in Fig. P3.33 is realized with transistors having the 0.18-μm CMOS parameters in Table 1.5. All gate lengths are , , and . The differential pair is perfectly...

The differential pair circuit shown in Fig. P3.33 is realized with transistors having the 0.18-μm CMOS parameters in Table 1.5. All gate lengths are , , and . The differential pair is perfectly symmetric. The device widths are related by and .

a. Select the NMOS device widths so that .

b. Select the PMOS device widths so that .

c. Estimate the differential small-signal gain of the circuit, .