The delay element seen in Fig XXXXXXXXXXdoesn't use a reference voltage. Show how this element can be used in the VCDL of Fig XXXXXXXXXXNote that the input capacitance of this delay stage is twice as...

The delay element seen in Fig. 19.79 doesn't use a reference voltage. Show how this element can be used in the VCDL of Fig. 19.61.Note that the input capacitance of this delay stage is twice as large as the input capacitance of the element in Fig. 19.61 (and so you may have to use fewer stages to attain the same overall delay). How does the NMOS gate potential change with the inputs/outputs switching? Why? Is the output amplitude a function of VDD?