The combination of two enhancements is considered to boost the performance of a chip multiprocessor. The enhancements are: (1) adding more cores or (2) adding more shared level 2 cache. The base chip...

The combination of two enhancements is considered to boost the performance of a chip multiprocessor. The enhancements are: (1) adding more cores or (2) adding more shared level 2 cache. The base chip has three cores and nine L2 cache banks. The L2 cache size can be incrementally increased by adding cache banks, and each cache bank uses three times the area of a core. Here is what we also know from all kinds of sources:

(i) 60% of the workload can be fully parallelized, the rest cannot;

(ii) the core stall time due to L2 misses accounts for 30% of each core’s execution time in the base configuration with four cache banks and four cores;

(iii) it is suspected that the amount of shared L2 cache per core should remain constant in order to keep the same miss rate;

(iv) simulations have also determined that the miss rate of L2 decreases as the square root of its size per core. A conjecture is that the stall time in each core will also decrease as the square root of L2 size per cores.