The CMOS differential pair circuit shown in Fig. P3.29 is to be designed to have a differential gain of 4 V/V and a power consumption of 1 mW. The transistors should be biased to have a and should...

The CMOS differential pair circuit shown in Fig. P3.29 is to be designed to have a differential gain of 4 V/V and a power consumption of 1 mW. The transistors should be biased to have a and should have a gate length of 0.25 μm. Using the 0.18-μm CMOS parameters in Table 1.5, determine the widths of the transistors and the values of and . Compare your results with SPICE.