The circuit of Fig. P5.21 is the dual of that of Fig. 5.16 because we can obtain it from the former by interchanging pFETs with nFETs and vice versa, as well as interchanging the power-supply...

The circuit of Fig. P5.21 is the dual of that of Fig. 5.16 because we can obtain it from the former by interchanging pFETs with nFETs and vice versa, as well as interchanging the power-supply polarities (omitted for simplicity, the biasing circuitry is modeled via the dc sources V1, V2, and V3). (a) Assuming k9 n 5 200 A/V2 , k9 p 5 80 A/V2 , Vtn 5 2Vtp 5 0.5 V, 9 n 5 0.02 m/V, 9 p 5 0.04 m/V, and L 5 0.75 m, specify W1 through W11 for ID9 5 ID10 5 100 A, ID11 5 80 A, and VOV # 0.2 V throughout. (b) Assuming


5 0.1 throughout, fi nd the gain and the output resistance. (c) If V2 and V3 are biasing the pFETs right at the EOS and the circuit is powered from 61.65-V supplies, fi nd the IVR and the OVS.