The circuit of Fig. P4.83 uses the nMOS mirror M1-M2 to sink the current I1 from the load LD1, and the pMOS mirror M4-M5 to source the current I2 to the load LD2. The nMOS mirror is biased by the...

The circuit of Fig. P4.83 uses the nMOS mirror M1-M2 to sink the current I1 from the load LD1, and the pMOS mirror M4-M5 to source the current I2 to the load LD2. The nMOS mirror is biased by the input source II , and it comprises an additional FET, M3, to establish the current I3 needed to bias the pMOS mirror. Assume the process parameters to be Vt n 5 2Vt p 5 0.5 V, k9 n 5 2.5k9 p 5 100 A/ V 2 , and 9 p 5 9 n 5 0.05 V 21 . (a) If II 5 50 A, specify WyL ratios for M1, M3, and M4 so that I3 5 II and VOV4 5 VOV1 5 0.25 V. (b) Specify W2 and L2 so that at dc balance M2 sinks I1 5 250 A with ro2 5 100 kV. (c) Specify W5 and L5 so that at dc balance M5 sources I5 5 100 A with ro5 5 100 kV.