The circuit of Fig. P4.5 is the CMOS counterpart of the bipolar version of, and its analysis follows a line of reasoning similar to Example 4.1. Let M1 have kn 5 400 A/V2 , Vt n 5 1.0 V, and n 5 1y(25 V), and let M2 have kp 5 175 A/V2 , Vt p 5 20.75 V, and p 5 1y(20 V).
(a) If VDD 5 5 V and the FETs are biased at 200 A, estimate vO(min) and vO(max), the lower and upper limits of the linear output swing (to simplify your calculations, assume p 5 n 5 0 in this step).
(b) Find VGS and VSG so that the output node is biased right in the middle of the linear range.
(c) Find the gain a 5 voyvi .
(d) How is VO affected if VGS is 10 mV higher than the value calculated in the example?
(e) What if VSG is 10 mV higher than the calculated value?
(f) If vi 5 Vim cos t, estimate the maximum value of Vim for which the output is still a relatively undistorted sinewave. Justify any approximations you may be making.