The circuit of Fig XXXXXXXXXXwith and is realized with the technology in Table 1.5. Switches are NMOS devices with a gate voltage and the schematic’s “ground” voltage located above the opamp’s lower...

The circuit of Fig. 14.29 with and is realized with the technology in Table 1.5. Switches are NMOS devices with a gate voltage and the schematic’s “ground” voltage located above the opamp’s lower supply. Find the size of switches required to ensure a dc offset of less than 5 mV due to charge injection. If all switches are the same size, and allowing 5 time constants for complete settling, what is the resulting settling time of switched capacitor ?