The circuit made up for transistors M3 through M8 in Fig. P4.107 is designed to establish the quiescent current of the CS pair M1-M2 at an acceptable level while retaining the inherently wide OVS of...

The circuit made up for transistors M3 through M8 in Fig. P4.107 is designed to establish the quiescent current of the CS pair M1-M2 at an acceptable level while retaining the inherently wide OVS of the CMOS inverter. Assume all FETs have Vt 5 0.75 V, and let VDD 5 2VSS 5 5 V. (a) Assuming M3 through M8 have k 5 1.6 mA/V2 , fi nd the values of the biasing voltages VG6 and VG8 that will cause M3 through M8 to draw a current of 50 A each for vI 5 0. (b) Find k1 and k2 so that in standby ID1 5 ID2 5 0.25 mA. (c) Find the limits vO(max) and vO(min) of the OVS if RL 5 2 kV. What are the corresponding values of vI ? (d) Find vO for vI 5 61 V.