The CG circuit of Fig. P3.66 has VDD 5 2VSS 5 10 V, and the FET has k 5 1.0 mA/V2 , Vt 5 1.0 V, and 5 0. (a) Specify R1 and R2 to ensure ID 5 2 mA and to bias the drain halfway between (VS 1 VOV) and...

The CG circuit of Fig. P3.66 has VDD 5 2VSS 5 10 V, and the FET has k 5 1.0 mA/V2 , Vt 5 1.0 V, and 5 0. (a) Specify R1 and R2 to ensure ID 5 2 mA and to bias the drain halfway between (VS 1 VOV) and VDD. (b) Specify R3 and C for a gain voyvsig 5 12 V/V at a signal frequency of 10 kHz. Hint: consider fi rst the gain from vsig to vs , and then from vs to vo, where vs is the signal at the source terminal of the FET.