The CFA closed-loop bandwidth of Eq. (7.27) was derived under the assumption of an ideal input voltage buffer across the inputs. However, a reallife buffer will exhibit a small output resistance Rn,...

The CFA closed-loop bandwidth of Eq. (7.27) was derived under the assumption of an ideal input voltage buffer across the inputs. However, a reallife buffer will exhibit a small output resistance Rn, as shown in Fig. P7.10. (a) Using the results of Problem 5.38, show that Eq. (7.27) still holds, provided we let R2 → R2 1 Rn(11 R2yR1). (b) What is the actual closed-loop bandwidth of the circuit of Example 7.7? (c) How would you lower R2 to retain the same bandwidth (60 MHz), and R1 to retain the same gain (10 V/V)?