The Black Box takes 3 digital inputs (I1, I2 and I3) and generates the values of 2 digital outputs (Q1 and Q2) based on these. There is an additional input (I4) which makes the black box operate with the inverse logic to usual, that is – it inverts the values of Q1 and Q2 which would usually be displayed for a given state of I1, I2 and I3. There is one additional output which is on when none of the other outputs (Q1 or Q2) are activated, to show that the unit is operational but outputting two zero values. The input and output details are as follows: Digital Inputs: I1: Digital Input 1 I2: Digital Input 2 I3: Digital Input 3 I4: Inverse Operation Option Digital Outputs: Q1: Digital Output 1 Q2: Digital Output 2 Q3: Q1 and Q2 both zero The code is to be programmed in FBD (Functional Block Diagram) language using the template file provided.
Microsoft Word - Assignment 2 2021 v1p0 variation 6.docx ELE1301 – Computer Engineering Design Assignment 1 Logic Implementation Date Due: Monday, 22 March 2021, 11.55pm AEST Penalty for late submission: 10% per working day late Task: Your task is to program the code for “The Black Box”. You have been given a template code file into which your code will be placed. The Black Box takes 3 digital inputs (I1, I2 and I3) and generates the values of 2 digital outputs (Q1 and Q2) based on these. There is an additional input (I4) which makes the black box operate with the inverse logic to usual, that is – it inverts the values of Q1 and Q2 which would usually be displayed for a given state of I1, I2 and I3. There is one additional output which is on when none of the other outputs (Q1 or Q2) are activated, to show that the unit is operational but outputting two zero values. The input and output details are as follows: Digital Inputs: I1: Digital Input 1 I2: Digital Input 2 I3: Digital Input 3 I4: Inverse Operation Option Digital Outputs: Q1: Digital Output 1 Q2: Digital Output 2 Q3: Q1 and Q2 both zero The code is to be programmed in FBD (Functional Block Diagram) language using the template file provided. Note: The preferred version of software is ZelioSoft 2 v 5.3.1 ELE1301 – Computer Engineering Black Box Operation Logic You have been given the following operational parameters for your Black Box Operation: I1 I2 I3 Q1 Q2 0 0 0 1 0 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 Note that these are the states Q1 and Q2 should indicate while the inverse operation button is not selected. You will need to create a new truth table including the additional inputs, outputs and operation. That is, your truth table will include 4 inputs and 3 outputs. The logic simplification that you complete should be based solely on the truth table. If you notice a more efficient way of completing the task you are welcome to submit that also but please note that the marking rubric (attached) allocates marks towards the completion of the truth table and the subsequent logic simplification process. ELE1301 – Computer Engineering Report: You must submit a report that meets the following minimum objectives: A brief problem statement. Documentation of assumptions or clarifications around the task (if any). A truth table showing every input case and the status of the output bits at each value. Full, unsimplified logic equations for each output. For each output, a Karnaugh map and completed simplification process, giving the simplified expression as the result. A logic diagram for the simplified logic expression for each output. This should use the American Standard symbols as shown in Figure 4.26 of the study material. You may use AND, OR, XOR and NOT gates. (May be hand drawn and scanned into the document.) Implementation of the simplified equations in the software using AND, OR, XOR and NOT gates. Screen shots of two cases demonstrating the testing of the operation of the logic using the simulator function of the program and the provided template. The two cases are to be where I1, I2, I3, and I4 are all on, and where I1, I2, and I3 are on while I4 is off. Documentation of the testing process undertaken and the full results of the testing process, which may be tabularised. Note that this must be included in the results section not with the truth table at the beginning of the report. Notes: Refer to the study material, the tutorial activities and the learning activities for guidance. The code must be implemented into the provided template. The template includes a Supervision window to allow simple testing in Simulation mode. Refer to the attached Marking Rubric, which indicates the criteria that your submission will be assessed against. Submission: You are to submit both your report and the ZelioSoft 2 file to StudyDesk for assessment. Do NOT submit any of your assignment by email or hardcopy, unless approved by the examiner. ELE1301 Design Assignment 1 Marking Rubric Criteria Marks (of Total 250) Insufficient Limited Developing Effective Comprehensive Problem Statement 10 Not included. Problem Statement is mostly inaccurate or deficient. Problem Statement contains some inaccuracies or deficiencies. Problem Statement closely defines the program objectives. Problem Statement accurately defines the program objectives. Truth Table 20 Not included. Truth table somewhat defines the logic of all outputs for at least one state. Truth table somewhat defines the logic of all outputs for most states. Truth table correctly defines the logic of all outputs for most states. Truth table correctly defines the logic of all outputs for each state. Unsimplified Logic Expressions 20 Not included. An attempt has been made to list the full logic expressions in canonical form, though major errors are present. Lists, for each output, the full logic expressions in canonical form with substantial errors. Lists, for each output, the full logic expressions in canonical form with slight errors. Correctly lists, for each output, the full logic expressions in canonical form. Karnaugh Maps 20 Not included. The Karnaugh maps for some outputs have been created and populated. Significant errors exist. The Karnaugh maps for most outputs have been created, populated and grouped. Significant errors exist. The Karnaugh maps for most outputs have been accurately created, populated and grouped. Minor errors exist. The Karnaugh maps for each output have been accurately created, populated and grouped. Simplified Logic Expressions 20 Not included. The simplified logic expressions were either not obtained from the Karnaugh maps or had substantial errors. The simplified logic expressions from the Karnaugh map have been generally correctly obtained. The simplified logic expressions from the Karnaugh map have been generally correctly obtained and, where sensible, simplified using Boolean logic. A rationale is given for any decisions made. The simplified logic expressions from the Karnaugh map have been correctly obtained and, where sensible, simplified using Boolean logic. A rationale is given for any decisions made. Logic Diagrams 30 Not included. An attempt at drawing the simplified logic expressions obtained in the previous question is included. Use of non-standard gates or symbols is present, or there are substantial problems with the diagrams. The simplified logic expressions obtained in the previous question are correctly drawn using standard gate symbols with some significant errors or inconsistencies. The simplified logic expressions obtained in the previous question are correctly drawn using standard gate symbols with some slight errors or inconsistencies. The simplified logic expressions obtained in the previous question are correctly drawn using standard gate symbols. Use of Template 10 Not included. The program did not use the provided template or had major errors with the I/O allocations specified. The program used the provided template and met the I/O specifications with some significant errors or inconsistencies. The program used the provided template and met the I/O specifications with some slight errors or inconsistencies. The program used the provided template and met the I/O specifications. Criteria Marks (of Total 250) Insufficient Limited Developing Effective Comprehensive FBD Code 30 Not included. The logic for each output is implemented as per the logic derived previously with significant errors. The logic for each output is correctly implemented as per the logic derived previously with minor errors. The logic for each output is correctly implemented as per the logic derived previously. No obvious attempt was made to simplify or optimise during the implementation. The logic for each output is correctly implemented as per the logic derived previously. Where practical, logic has been simplified and optimised, such as re-using already available logic. Readability 20 Not included. The FBD code is generally not well laid out and is difficult to follow. The FBD code is generally not consistently laid out or can be difficult to follow in places. A reasonable effort has been taken to make the FBD code layout as readable as possible. Comments, where used, are useful. Some consideration has been given to the layout of logic components. Suitable effort has been taken to make the FBD code layout as readable as possible. Comments, where used, are useful, and the layout of logic components is carefully considered. Code 30 Not included. The code functions and meets the specification for at least one output. The code functions and meets the specification for around half of the outputs. The code is fully functional and meets the specification for most outputs. The code is fully functional and meets the specification for all outputs. Results 20 Not included. The truth table was included but did not adequately demonstrate that the required operation had been tested. The results table shows that testing has been undertaken for each input state, ensuring operation in alignment with the truth table with several errors. The results table shows that testing has been undertaken for each input state, ensuring operation in alignment with the truth table with