Task: Modify the Laser Circuit FSM to output x for 25 ns, assuming T clk = 5 ns. Given VHDL code for the Laser Circuit FSM: library ieee; use ieee.std_logic_1164.all; entity LaserTimer is port ( b: in...

Task:
Modify the Laser Circuit FSM to output x for 25 ns, assuming T_clk
= 5 ns.

Given VHDL code for the Laser Circuit FSM:

library ieee;
use ieee.std_logic_1164.all;

entity LaserTimer is
port ( b: in std_logic;
x : out std_logic;
clk, rst : in std_logic;
);
end LaserTimer;

architecture behavior of LaserTimer is
type statetype is
(S_Off, S_On1, S_On2, S_On3);
signal currentState, nextState:
statetype;

begin
statereg: process(clk, rst)
begin
if (rst=’1’) then
currentstate <=>
elsif (clk=’1’ and clk’event) then
currentstate <=>
end if;
end process;

comblogic: process (currentstate, b)
begin
case currentstate is
when S_Off =>
x <=>
if (b=’0’) then
nextstate <=>
else
nextstate <=>
end if;
when S_On1 =>
x <=>
nextstate <=>
when S_On2 =>
x <=>
nextstate <=>
when S_On3 =>
x <=>
nextstate <=>
end case;
end process;
end behavior;