Task #1: In the last lab, you were requested to describe a half-adder using Verilog HDL. In this task you will implement a 1-bit full adder by instantiating two half adders as illustrated in the...

Extracted text: Task #1: In the last lab, you were requested to describe a half-adder using Verilog HDL. In this task you will implement a 1-bit full adder by instantiating two half adders as illustrated in the figure below (Steps will be shown to you by the lab instructor). Cin Sum Half Adder Half Adder Cout 1. Write a Verilog module that describes a l-bit full adder using Verilog Structural modeling. Use module instantiation, just as discussed in the class. You will have to instantiate two half adders inside the full adder module. 2. Implement the Verilog module on the platform FPGA.