Suppose the FETs of are fabricated in a process for which we can approximate Cgd ù 0.25W fF, Qn ù 1.75WVOV fC, and k 5 125W A/V2 , where W is the channel width, in m, and VOV is the overdrive voltage,...

Suppose the FETs of are fabricated in a process for which we can approximate Cgd ù 0.25W fF, Qn ù 1.75WVOV fC, and k 5 125W A/V2 , where W is the channel width, in m, and VOV is the overdrive voltage, in V. Moreover, let Vt 5 0.5 V, and assume the gate voltages alternate between 62.5 V. (a) Specify W1 so that rDS1 5 500 V for vI 5 0. What is rDS1 at vI 5 0.5 V? At vI 5 20.5 V? (b) If Ctot 5 750 fF, fi nd the error in vO due to clock feedthrough for vI 5 0, 0.5 V, and 20.5 V. (c) Repeat part (b) but for charge injection with a 5 0.5. (d) Specify W2 so as to cancel out the clock feedthrough due to M1. (e) What can you say about charge injection cancellation if a 5 0.5? If a 5 1?