Suppose that a computer has a processor with two L1 caches, one for instructions and one for data, and an L2 cache. Let t be the access time for the two L1 caches. The miss penalties are approximately...

Suppose that a computer has a processor with two L1 caches, one for instructions and one for data, and an L2 cache. Let t be the access time for the two L1 caches. The miss penalties are approximately 20t for transferring a block from L2 to L1, and 100t for transferring a block from the main memory to L2. For the purpose of this problem, assume that the hit rates are the same for instructions and data and that the hit rates in the L1 and L2 caches are 0.92 and 0.88, respectively. [CO-4, BT-3 (Applying)]

Q: Consider the following change to the memory hierarchy. The L2 cache is removed. What is the average memory access time as seen by the processor in this case?

Q: What is the average access time as seen by the processor?