Suppose that a bus has 16 data lines and requires 4 cycles of 250 nsecs each to transfer data. The bandwidth of this bus would be 2 Megabytes/sec. If the cycle time of the bus was reduced to 125 nsecs...

Extracted text: Suppose that a bus has 16 data lines and requires 4 cycles of 250 nsecs each to transfer data. The bandwidth of this bus would be 2 Megabytes/sec. If the cycle time of the bus was reduced to 125 nsecs and the number of cycles required for transfer is doubled, what would the bandwidth of the bus? Select one: a.2 Megabytes/sec b.1 Megabytes/sec c.4 Megabytes/sec d.8 Megabytes/sec


Extracted text: In a CISC processor, simple instructions are executed in 4 cycles and complex instructions take 9 cycles. The cycle time for this CISC processor is 102 ns. For a program of 1,000,000 instructions, where 80% of the executed instructions are simple and the other 20% are complex, determine the time it takes to run the program in the RISC processor. Select one: a.0.5 s b.0.27 s c.0.24 s d.0.48 s e.0.51 s