Shown in Fig. P4.48 is the pMOSFET realization of the SC pair concept. Let VSS 5 2VDD 5 5 V, RD1 5 RD2 5 10 kV, ISS 5 0.5 mA, and RSS 5 `. Moreover, let the FETs have k 5 1 mA/V2 , Vt 5 20.5 V, 5 0,...

Shown in Fig. P4.48 is the pMOSFET realization of the SC pair concept. Let VSS 5 2VDD 5 5 V, RD1 5 RD2 5 10 kV, ISS 5 0.5 mA, and RSS 5 `. Moreover, let the FETs have k 5 1 mA/V2 , Vt 5 20.5 V, 5 0, and 5 0. (a) If vI1 5 vI2 5 0 V, fi nd vO1, vO2, and vS, the voltage at the sources. What is the gain vodyvid? (b) If the inputs are tied together and are driven by a common voltage vIC, what is the lower limit vIC(min) for which the FETs are still saturated? (c) Find the vID range needed to steer ISS from one side to the other of the SC pair, as well as the values of vO1, vO2, and vS at the extremes of this range. (d) Find vID so that vOD 5 4 V.