Section 4.5.3 discusses the difference between various failure models. Compare the reliability of a 1-bit TMR system under the following failure model assumptions: (a) The failures are always s-a-1....

Section 4.5.3 discusses the difference between various failure models. Compare the reliability of a 1-bit TMR system under the following failure model assumptions:

(a) The failures are always s-a-1.

(b) The failures are always s-a-0.

(c) The circuits fail so that they always give the complement of the correct output.

(d) The circuits fail at a transient rate lt and produce the complement of the correct output.