IEEE Paper Template in A4 (V1)
Power Reduction and Management Techniques with
Multicore System
First Author
#1
, Second Author
*2
, Third Author
#3
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First-Third Department, First-Third University
Address Including Country Name
1
[email protected]
3
[email protected]
*
Second Company
Address Including Country Name
2
[email protected]
Abstract— This paper presents a survey on
power reduction and management techniques
with Multicore system. A multi-core system is
the system where multiple systems or we should
say CPU works together on a single chip, in an
integrated form. In this architecture, the
combined logic of the required processors is
implemented as a unit of logic in a single
physical processor. These form a package which
is based on “Integrated Circuit”. Another term
used for this is known as a “die”. There are a lot
of benefits of using Multicore systems. More
tasks can be done using multi core systems with
improved system performance. This technology
is being used in various servers, mobile
computing, desktop machines, military,
embedded systems, signal processing industry,
etc. Its use is increasing tremendously because of
the need for more and faster performance.
Parallel processing helps in achieving the goal by
combining and working on parallel resources.
All this benefits does not come alone. Pros and
cons are associated with this technology too. A
lot of power is consumed in multi core systems
because this system executes multiple processes.
So a Power reduction and management
technique is required so that the resources can
be utilized in an optimum manner while
maximizing the profit. Power management deals
with the generation of power in terms of voltage
and its management so that the requirements to
execute and control a system can be full-filled.
With the increasing consumption of power, an
efficient technique is required so that the overall
performance of the system can be increased. In
this paper, a number of power reduction and
management techniques will be discussed. Both,
static as well as dynamic techniques will be
discussed. Static techniques are applied at the
design time; various simulation tools have been
used keeping in mind the varying configuration
of hardware as well as software. Dynamic
techniques are applied at run-time. The main
focus of applying dynamic technique is to
decrease the use of power at CPU level. It also
helps in reducing the energy consumption of the
whole system. The design should be included in
the system’s design itself so that the efficiency of
the system can be improved.
A power management technique is required so
that a balance can be achieved between power
reduction and the performance. A trade-off is
required between both of the mentioned terms.
If the priority is the high performance then
obviously more power will be consumed to
achieve the output. If the power consumption
needs to be reduced then it will definitely affect
the overall performance of the system.
Different power management techniques are
discussed in this paper for reducing power
management in the computer systems. Static as
well as dynamic techniques are discussed in this
paper. Various simulation modules and tools are
used for evaluating the performance of the
system.
Keywords— Power Management, Power
Reduction, Linear Regulator.
INTRODUCTION
As a result of hitting the wall of moors' law, as the
number of transistor and cores increased, the
performance and power consumption increased. It
becomes very important to find ways to reduce this
power, and heat dissipation. These days, on a single
chip, many numbers of transistors can be combined
and integrated. This process requires high power
consumption. The system consuming high power
gives a better performance so a balance is required
between power consumption and performance of
the system. A voltage regulator is required to
achieve this balance so that power consumption can
be minimized and efficiency of the system can be
increased. Overall the system will work in an
efficient manner, maintaining optimum resource
utilization.
Different techniques are discussed in this paper
regarding voltage regulation and then a comparison
is made to find out the appropriate technique.
The figure drawn below shows the function of a
voltage regulator:
Control
Various techniques based on voltage regulation are
discussed in this paper.
CHALLENGES & PITFALLS of POWER
REDUCTION with MULTICORE
The "power wall" [1] has made it compulsory for
the chip designers and system architects so that they
design with slighter borders among nominal and
worst-case operating points. There are higher
chances of vulnerability for the processors to
inductive noise in smaller voltage margins. Even a
high energy particle can cause an event which can
modify the normal processing. Lower power is
achieved at the expense of tolerating occasional
errors [2] that the processor is able to recover from.
Alternatively, a slight performance hit is incurred in
order to proactively prevent a circuit failure [3].
System and chip designing consists of dynamic
power and thermal management techniques. These
techniques helps a lot in changing the routine
configuration at run time if need arises. The main
reason for implementing these changes is to
improve the performance of the overall system. But
there are various challenges and pitfalls in
implementing this dynamic architecture. Few
challenges are discussed below:
How to verify that the systems will always full-fill
the required specification?
How the configuration can be tested against
malicious attacks?
What are the possible methods the system must
possess to ensure security requirements regarding to
future enhancements?
Unregulated
Voltage
Semiconductor
switches
Regulated
Voltage
DYNAMIC POWER MANAGEMENT
Baseline power management algorithms will be
discussed in this section.
Dynamic Voltage-Frequency Scaling and Power
Gating
Dynamic power gating (DPG) algorithms are
designed in such a way so that power can be
reduced by cutting off the power supply to idle
resources. This algorithm is very effective for
power saving if accuracy of the system is
maintained throughout the process.
Fig. 1. Hierarchical management & control
The above drawn figure shows the hierarchical
view of the dynamic management and control.
Distributed monitor architecture is required in this
design specification, power performance and other
measuring factors regarding reliability of the
system will be acknowledged by this monitor.
There may be local monitors configured in devices.
The main advantage of these local monitor is that
immediate action can be taken if required. Few
examples are: instruction fetch-gating [12], and
dynamic frequency scaling in response to voltage
dips [3]. Global controller controls the coordination
among the local controllers. It follows the
instruction given by the system level controller. For
e.g., in case of power emergency, the main
controller, which is system level controller,
instructs the global controller and other chips to
work with limited power supply. It is the
responsibility of Global controller to actuate the
dynamic voltage frequency scaling and power
gating knob so that the whole processing can be
done within the limited power supply. The
performance cost remains minimum in this
scenario.
Multicore systems generally consume more power
than other. Following are the few parameters on
which this thing will be proved:
1. Lower frequency: Since power is
proportional to frequency cube square **,
halving the frequency reduces speed by 2x
but power by 8x, making it 4x energy
efficient.
2. Less speculation: FAST, aggressive cores
tend to be more speculative because they
never waste time in waiting for data; they
just predict the value and do the work in the
hope that their prediction will be correct.
This does improve performance but
incorrect predictions lead to wasted work.
3. Lower flip-flop power. This one is a bit
subtle. FAST cores tend to have deeper
pipelines for high performance. The more
the pipeline stages, the higher the number of
flip-flops in the core, which leads to higher
wasted energy in flops.
So, the question is do Multicore system really saves
energy? In the following section, the answer of this
question will be evaluated. There is no specific
answer for this question. An analysis needs to be
done for this scenario. A proper configuration needs
to be done for multi core system. Each core is the
multi core system needs to be configured as energy
efficient, only then the multi core system will save
energy. Following two measuring factors will be
Global Controller
System-level controller
Memory Hierarchy
Interconnect
core core core
used for this analysis purpose: one main factor is
the speed and the other one is the energy. Let us
suppose a care which is fast enough to run at 10 W,
execution of the core completes in 10 sec of time.
So the total energy would be the product of power
and time. In this scenario, the total energy will be
10 * 10 = 100J.
Now we will compare this with another core which
consists of two fast cores. As there are two cores in
this configuration, so the power would be double
i.e. 20 W in the given scenario. Time to execute the
system will be reduced to half of the original
configuration, i.e. 5 sec. But energy would be the
same, i.e. 100 J. So, no saving is there even with
using multi core configuration. The only benefit in
this configuration is reduction of execution time. If
time would have also been same, then there would
not be any benefit of using multi core systems.
.
Consider another scenario, in this configuration; a
slow core would be used in the configuration
instead of the fast core. Let us assume that the
power consumes 5 W and the time required for
execution is 15 sec. Total energy would be equal to
the product of power and the execution time. So the
total energy would be 75J. Now it depends upon the
individual’s preference. The configuration...