RESET PRESENT | NEXT STATE | OUTPUT W = 0 W = 1 00 W =1 State A State B STATE W = 0 A Output Z=0 00 01 01 01 Output Z=0 00 W = 0 10 00 10 DD 1 11 DD D W = 0 W = 1 State C Output Z=1 W =1 Figure 3:...

1) Generate and simulate the VHDL codes in Altera Quartus II.

2) Observe and provide your observation and conclusion based the waveform.

3) Sketch and discuss its equivalent based Mealy Machine state in discussion.

RESET<br>PRESENT | NEXT STATE | OUTPUT<br>W = 0 W = 1<br>00<br>W =1<br>State A<br>State B<br>STATE<br>W = 0<br>A<br>Output<br>Z=0<br>00<br>01<br>01<br>01<br>Output<br>Z=0<br>00<br>W = 0<br>10<br>00<br>10<br>DD<br>1<br>11<br>DD<br>D<br>W = 0<br>W = 1<br>State C<br>Output<br>Z=1<br>W =1<br>Figure 3: Moore Machine<br>

Extracted text: RESET PRESENT | NEXT STATE | OUTPUT W = 0 W = 1 00 W =1 State A State B STATE W = 0 A Output Z=0 00 01 01 01 Output Z=0 00 W = 0 10 00 10 DD 1 11 DD D W = 0 W = 1 State C Output Z=1 W =1 Figure 3: Moore Machine

Jun 11, 2022

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RESET PRESENT | NEXT STATE | OUTPUT W = 0 W = 1 00 W =1 State A State B STATE W = 0 A Output Z=0 00 01 01 01 Output Z=0 00 W = 0 10 00 10 DD 1 11 DD D W = 0 W = 1 State C Output Z=1 W =1 Figure 3:...

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