Repeat Problem 14.20, but this time size the switches to ensure a settling time of 40 ns. Find the resulting dc offset due to charge injection. What sampling-time uncertainty can be tolerated for a...

Repeat Problem 14.20, but this time size the switches to ensure a settling time of 40 ns. Find the resulting dc offset due to charge injection.

What sampling-time uncertainty can be tolerated for a 16-bit A/D converter operating on an input signal from 0–20 ?