SR latch is one of the simplest sequential circuits, which is composed of two cross-coupled NOR gates, as shown below. Select all TRUE statements. a If R = 1 and S = 1, Both NOR gates produce the...

If R = 1 and S = 1, Both NOR gates produce the FALSE outputs. That is an invalid state.

If R = 0 and S = 0, this circuit will remember the previous value (or state) Q and Q_complement.

If R = 0 and S = 1, it produces a TRUE output on Q.

If R = 1 and S = 0, it produces a FALSE output on Q.