Question 7 timescale Ins / lps module ha (input a, b, output sum, carry); assign sum-a^b; assign carry-Da&b; endmodule timescale Ins / 1ps module testbench (); reg a, b; wire sum, carry; integer i; ha...

Extracted text: Question 7 timescale Ins / lps module ha (input a, b, output sum, carry); assign sum-a^b; assign carry-Da&b; endmodule timescale Ins / 1ps module testbench (); reg a, b; wire sum, carry; integer i; ha dt (.a(a), .b(b), .sum (sum), .carry (carry)) : initial begin a-0; b-0; Smonitor ("a-0b b-0b sum-40b carry-40b", a, b, sum, carry); for (i-0; i<4; i="i+l)begin" {a,b}="i;" #10;="" end="" end="" initial="" #40="" $finish;="" endmodule="" which="" of="" the="" following="" is="" true="" for="" the="" two="" verilog="" codes="" above?="" 1.="" "sum"="" is="" equal="" to="" "a="" xnor="" b".="" ii.="" the="" "testbench"="" part="" runs="" for="" 40="" nano="" seconds.="" iii.="" gate="" design="" level="" is="" used="" in="" the="" code.="" here="" to="" search="" f2="">


Extracted text: endmodule Which of the following is true for the two verilog codes above? 1. "sum" is equal to "a XNOR b". II. The "testbench" part runs for 40 nano seconds. III. Gate design level is used in the code. Your answer: O ,I O Only II Clear answer Back Complete test o search 99