Question 2 timescale lns / Ips module mux (1nput 10, Il, slct, output out): vire slct_n: vire out 1: vire out 2: not (slet_n, slet): and (out 1, 10, sict_n): and (out_2, I1, slct): or (out, out_1, out...

Extracted text: Question 2 timescale lns / Ips module mux (1nput 10, Il, slct, output out): vire slct_n: vire out 1: vire out 2: not (slet_n, slet): and (out 1, 10, sict_n): and (out_2, I1, slct): or (out, out_1, out 2): endmodule timescale ins/ ips module testbench (): reg 10, Il, slet: vire out: integer i: mux dt (.10 (10), 1 (11), .lct (slet), .out (out) ): initial begin 10-0: Il-0: slct-0: Cmonstor ("siet-tob 10-sob 11-sob out-tob", slet, 10, I1, out): for (1-0: icB: 1-1+1) begin (alet, 10, I1)-1: #10: end end initial endmodule Which of the following is true for the above 2 verilog codes? 1. Gate design level is used in the code. II. 2x1 Multiplexer is designed in the code. III. All nets in the codes must be defined in the "testbench" section.