Q7. Compare between synchronous and asynchronous reset * asynchronous reset must wait the negative clock edge before it takes effec asynchronous reset must wait the clock edge before it takes effect...

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Extracted text: Q7. Compare between synchronous and asynchronous reset * asynchronous reset must wait the negative clock edge before it takes effec asynchronous reset must wait the clock edge before it takes effect synchronous reset must wait the clock edge before it takes effect synchronous reset must wait the positive clock edge before it takes effect Q8. Logic synthesis is a process to simulation the hdl code to check the functionality inferring logic circuit only to FPGA devices generating a netlist for many target devices convert the HDL to logic circuit specific to target device/technology