Q2 (а) A student is required to design a DRAM chip with word size of 4 bits, with row and column address decoders limited to 6 input bits. What is the largest memory chip that the student can design...

Extracted text: Q2 (а) A student is required to design a DRAM chip with word size of 4 bits, with row and column address decoders limited to 6 input bits. What is the largest memory chip that the student can design under these restrictions? (i) (ii) How many decoder NAND gates does the student’s design save over one which uses a single large address decoder? (iii) What are the advantages and disadvantages of using DRAM compared to using SRAM? (b) Memory with read timing parameters described by Figure Q2b is used as part of a synchronous system, with input being fed directly from the outputs of registers with tpd = 5 ns (rising clock edge to stable output) and outputs being fed to a register with setup and hold times of ts = 3ns and th = 2ns respectively. State the maximum clock frequency at which it can be driven. ADDRESS CS CSHZ + 'AcS DATA OUT 'CSLZ LACS=12 ns (max.) 'CSLZ-3 ns (min.) tCSHZ=6 ns (max.) Figure Q2b. Continued overleaf Page 3 of 4 (c) Describe the benefit of using VHDL in the design of large-scale digital systems.