Q1.31 The circuit diagram for the following Verilog statement is: "timescale 1 ns /1 ps // time units / resolution module and_or_prop_delay( input A, B, C, D; Output D, E; wire w1; and G1 #30 (w1 A,...

Extracted text: Q1.31 The circuit diagram for the following Verilog statement is: "timescale 1 ns /1 ps // time units / resolution module and_or_prop_delay( input A, B, C, D; Output D, E; wire w1; and G1 #30 (w1 A, B); //Prop delay: 30 ns not G2 #10 (E, C); //Prop delay: 10 ns or G3 #20 (D, w1, E); //Prop delay: 20 ns endmodule w/ GI 30 ms Your answer: O Yes O No