Q1) The following two entity declarations contain two of the most common syntax errors made in VHDL. What are they? a) entity ckt_a is port ( J, K : in std_logic; CLK : in std_logic : out std logic;)...

Extracted text: Q1) The following two entity declarations contain two of the most common syntax errors made in VHDL. What are they? a) entity ckt_a is port ( J, K : in std_logic; CLK : in std_logic : out std logic;) end ckt_a; b) entity ckt_b is port ( mr_fluffy mux_ctrl byte_out end ckt_b; : in std logic_vector (15 downto 0); : in std logic_vector (3 downto 0); : out std logic_vector (3 downto 0);