Processor + timer. a) Specify an ISA model for processor + timer. Attention: the number of cycles for the execution of instructions varies. Just formulate live ness: at some instructions the timer...

Processor + timer.

a) Specify an ISA model for processor + timer. Attention: the number of cycles for the execution of instructions varies. Just formulate live ness: at some instructions the timer stops ticking.

b) Suppose you start the timer (by writing to cmsr) with value T= h counteri. Give upper and lower bounds for the number of instructions that can be executed before the timer stops ticking.

c) Assume the hardware is clocked at 1 GHz. How much time passes until the interrupt?

d) Specify and program a driver for the timer.