Problem statement: The specification here is to generate a set of outputs for given conditions of input combinations. The conditions specified are not following any defined function hence the logic...

Problem statement:

The specification here is to generate a set of outputs for given conditions of input combinations. The conditions specified are not following any defined function hence the logic must be derived using the digital realization techniques like K maps and Boolean algebra to achieve equations for implementation logic.
Assumptions:

Since given table does not cover any don’t care or ignore conditions, it is assumed inputs are always having a well-defined logic 1 or 0 and never goes X or Z.

Problem statement: The specification here is to generate a set of outputs for given conditions of input combinations. The conditions specified are not following any defined function hence the logic must be derived using the digital realization techniques like K maps and Boolean algebra to achieve equations for implementation logic. Assumptions: Since given table does not cover any don’t care or ignore conditions, it is assumed inputs are always having a well-defined logic 1 or 0 and never goes X or Z. Truth Table I1 I2 I3 I4 Q1 Q2 Q3 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 1 1 0 1 0 1 0 1 1 0 1 1 0 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 0 1 0 0 0 1 1 0 1 0 0 1 0 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 1 0 0 1 1 1 1 0 0 1 Un-simplified logic equations Q1 = I1’I2’I3’I4’ + I1’I2’I3 I4’ + I1’I2I3’ I4’ + I1’I2I3 I4’ + I1I2’I3’ I4’ + I1I2’I3 I4’ + I1I2I3 I4’ + I1I2I3’I4 Q2 = I1’I2I3’I4’ + I1I2’I3’I4’ + I1I2’I3I4’ + I1I2I3’I4’ + I1I2I3I4’ + I1’I2’I3’I4 + I1’I2’I3I4 + I1’I2I3I4 Q3 = Q1’Q2’ Simplified logic equations I1I2/I3I4 00 01 11 10 00 1 1 01 1 1 11 0 1 1 10 1 1 Q1 = I3I4’ + I1’I4’ + I2’I4’ + I1I2I3’I4 = (I3 + I1’ + I2’) I4’ + I1I2I3’I4 I1I2/I3I4 00 01 11 10 00 1 1 01 1 1 11 1 1 10 1 1 Q2 = I1I4’ + I1’I2’I4 + I1’I3I4 + I2I3’I4’ Q3 = Q1’Q2’ Implementation of simplified logic FBD: Testing Procedure: All input combinations were tested one by one for both outputs. The results were as expected as per the truth table mentioned above. Table below shows how all intermediate terms were produced for given inputs and reflected on outputs. I1I2I3I4 (I3 + I1’ + I2’) I4’ I1I2I3’I4 Q1 I1I4’ I1’I2’I4 I1’I3I4 I2I3’I4’ Q2 Q3 0000 1 0 1 0 0 0 0 0 0 0001 0 0 0 0 1 0 0 1 0 0010 1 0 1 0 0 0 0 0 0 0011 0 0 0 0 1 1 0 1 0 0100 1 0 1 0 0 0 1 1 0 0101 0 0 0 0 0 0 0 0 1 0110 1 0 1 0 0 0 0 0 0 0111 0 0 0 0 0 1 0 1 0 1000 1 0 1 1 0 0 0 1 0 1001 0 0 0 0 0 0 0 0 1 1010 1 0 1 1 0 0 0 1 0 1011 0 0 0 0 0 0 0 0 1 1100 0 0 0 1 0 0 1 1 0 1101 0 1 1 0 0 0 0 0 0 1110 1 0 1 1 0 0 0 1 0 1111 0 0 0 0 0 0 0 0 1